基于FPGA的VHDL语言m序列生成详解+源码

说 明

可控m序列产生器我分成四个小模块来做，M，M1，M2，M3分别对应为：m序列产生器、控制器、码长选择器、码速率选择器。

一、M: m序列产生器 这是该设计的核心部分，原理就是设计一个通用m序列产生子单元，然后由外部选择器来写入码型，码长等参数，加以循环可连接成任意长度的m序列产生器，其子单元结构如下： C(N) C(N-1) +

A(N) Q(N+1) Q(N) D

CP B(N) 如上图，若N=15，就有15个这样的子单元首尾相接。注意：开头和结尾的两个子单元会有所不同，因为首单元需要输入初值，尾单元要进行直通反馈，在程序里请多留意。 图中，主要部件是一个D触发器，Q(N+1)为上一级输出；Q(N)既是本级输出；CP为选择后的时钟脉冲；B(N)为本级参数选择控制；A(N)受控于B(N),决定本级输出Q(N)是否反馈（B(N)为1时反馈）； C（N）为本级反馈；C（N-1）为下一级反馈。具体原理参看m序列组成结构。 此外，本程序还加入了EN(发送控制)、RN(首单元置数)、SEL1(码长选择，即N的选择，N=2-15)、SEL2(码型选择，即正逆码选择)四个控制端，可满足设计要求。OP为码输出端。

二、M1：控制器 控制器主要是将外部的序列发送控制信号STA转换为EN和RN两个控制信号。其中，EN与STA的波形基本一致，只是它与CP进行

了同步处理；RN在EN为‘1’的头一个脉冲周期里置高电平，以达到为序列发生器的首端置数的目的。如果不清楚的话可以看一下它的模拟波形。（注意：STA要采用自锁定开关，高电平有效）

三、M2：码长选择 序列的码长选择既是N值的选择，码长=2**N-1。核心就是一个计数器，可从2计到15。按一次PUSH就可以自动加一（注意：按键建议采用自弹跳按键，如过需要软件清除按键震颤的话，我再做发给你），没有0，1两个状态。如果需要的话还可以扩展7段数码管的接口，以显示N值。

四、M3：码速率选择器 码的传输速率是靠CP来控制的，CP的频率就等于码元速率。这段程序包含一个倍频器，一个5分频的分频器，可把5MHZ的脉冲源CLK扩展成1MHZ和10MHZ。FSEL1、FSLE2、FSEL3分别在选择1、5、10MHZ时为高电平，其余两个为低，建议采用3选1单刀单掷开关。

M1--------------------------------------------------

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY CTRL IS PORT( CP,STA : IN STD_LOGIC; EN,RN : OUT STD_LOGIC );

END CTRL;

ARCHITECTURE a OF CTRL IS SIGNAL Q1,Q2 : STD_LOGIC; BEGIN PROCESS(CP) BEGIN IF CP’event AND CP=’1’ THEN Q2<=Q1; Q1<=STA; END IF; END PROCESS; EN<=Q1; RN<=Q1 AND NOT Q2; END a;

M2-------------------------------------------------

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY COUNTER IS PORT( PUSH,EN,RST : IN STD_LOGIC; SEL1 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) );

END COUNTER;

ARCHITECTURE a OF COUNTER IS SIGNAL B,C : STD_LOGIC; SIGNAL QN : STD_LOGIC_VECTOR(3 DOWNTO 0);

BEGIN

PROCESS(PUSH,C)

BEGIN

IF EN=’0’ THEN

IF C=’1’ THEN

QN<=”0010”; ELSEIF PUSH’EVENT AND PUSH=’1’ THEN QN<=QN+1; END IF; ELSE QN<=QN; END IF; END PROCESS; B<=’1’ WHEN QN=”0000” ELSE ‘0’; C<=B OR RST; SEL1<=QN; END a;

M3-----------------------------------

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY FP IS PORT(

CLK,FSEL1,FSEL2,FSEL3 : CP : );

END FP;

ARCHITECTURE a OF FP IS SIGNAL Q1,Q2,Q3,RST SIGNAL M1,M5,M10 SIGNAL QN BEGIN BP1 : BLOCK

IN STD_LOGIC;

OUT STD_LOGIC

: STD_LOGIC; : STD_LOGIC;

: STD_LOGIC_VECTOR(2 DOWNTO 0);

BEGIN

PROCESS(CLK,Q1) BEGIN

IF Q1=’1’ THEN

Q1<=’0’ ELSEIF CLK’EVENT AND CLK=’1’ THEN Q1<=’1’; END IF; END PROCESS; END BLOCK BP1;

BP2 : BLOCK

BEGIN

PROCESS(CLK,Q2) BEGIN

IF Q2=’1’ THEN

Q2<=’0’ ELSEIF CLK’EVENT AND CLK=’0’ THEN Q2<=’1’; END IF; END PROCESS; END BLOCK BP2; FP : BLOCK BEGIN PROCESS(CLK,RST) BEGIN IF RST=’1’ THEN QN<=”000”; ELSEIF CLK’EVENT AND CLK=’1’ THEN QN<=QN+1; END IF; END PROCESS; END BLOCK FP; Q3<=Q1 OR Q2; RST<=’1’ WHEN QN=”101” ELSE ‘0’; M1<=QN(2) AND FSEL1; M2<=CLK AND FSEL2; M3<=Q3 AND FSEL3; CP<=M1 OR M2 OR M3; END a;

M----------------------------------------

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY PN1 IS PORT( CP,SEL2,EN,RN : IN STD_LOGIC; SEL1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);

OP : OUT STD_LOGIC ); END PN1;

ARCHITECTURE a OF PN1 IS SIGNAL Q, A,B,C : STD_LOGIC_VECTOR(14 DOWNTO 0); SIGNAL SEL : STD_LOGIC_VECTOR(4 DOWNTO 0);

BEGIN SEL<=SEL1&SEL2; PROCESS (CP,SEL) BEGIN IF CP'event AND CP='1' THEN IF EN='0' THEN Q<=\ OP<=Q(0); ELSE Q(14)<=C(14) OR RN; B<=\ CASE SEL IS WHEN\ C(0)<=Q(0); B(1)<='1'; FOR I IN 1 TO 14 LOOP Q(I-1)<=Q(I); A(I)<=Q(I) AND B(I); C(I)<=C(I-1) XOR A(I); END LOOP; OP<=Q(0); WHEN\ C(0)<=Q(0); B(14)<='1'; FOR I IN 1 TO 14 LOOP Q(I-1)<=Q(I); A(I)<=Q(I) AND B(I); C(I)<=C(I-1) XOR A(I); END LOOP; OP<=Q(0); WHEN\ C(1)<=Q(1); B(2)<='1'; B(7)<='1'; B(11)<='1'; FOR I IN 2 TO 14 LOOP

Q(I-1)<=Q(I); A(I)<=Q(I) AND B(I); C(I)<=C(I-1) XOR A(I); END LOOP; OP<=Q(1); WHEN\ C(1)<=Q(1); B(5)<='1'; B(9) <='1'; B(14) <='1'; FOR I IN 2 TO 14 LOOP Q(I-1)<=Q(I); A(I)<=Q(I) AND B(I); C(I)<=C(I-1) XOR A(I); END LOOP; OP<=Q(1); WHEN\ C(2) <=Q(2); B(3) <='1'; B(5) <='1'; B(6) <='1'; FOR I IN 3 TO 14 LOOP Q(I-1)<=Q(I); A(I)<=Q(I) AND B(I); C(I)<=C(I-1) XOR A(I); END LOOP; OP<=Q(2); WHEN\ C(2) <=Q(2); B(11) <='1'; B(12) <='1'; B(14) <='1'; FOR I IN 3 TO 14 LOOP Q(I-1)<=Q(I); A(I)<=Q(I) AND B(I); C(I)<=C(I-1) XOR A(I); END LOOP; OP<=Q(2); WHEN\ C(3) <=Q(3); B(4) <='1'; B(7) <='1'; B(9) <='1'; FOR I IN 4 TO 14 LOOP Q(I-1)<=Q(I); A(I)<=Q(I) AND B(I);

C(I)<=C(I-1) XOR A(I); END LOOP; OP<=Q(3); WHEN\ C(3) <=Q(3); B(9) <='1'; B(11) <='1'; B(14) <='1'; FOR I IN 4 TO 14 LOOP Q(I-1)<=Q(I); A(I)<=Q(I) AND B(I); C(I)<=C(I-1) XOR A(I); END LOOP; OP<=Q(3); WHEN\ C(4) <=Q(4); B(6) <='1'; FOR I IN 5 TO 14 LOOP Q(I-1)<=Q(I); A(I)<=Q(I) AND B(I); C(I)<=C(I-1) XOR A(I); END LOOP; OP<=Q(4); WHEN\ C(4) <=Q(4); B(13) <='1'; FOR I IN 5 TO 14 LOOP Q(I-1)<=Q(I); A(I)<=Q(I) AND B(I); C(I)<=C(I-1) XOR A(I); END LOOP; OP<=Q(4); WHEN\ C(5) <=Q(5); B(8) <='1'; FOR I IN 6 TO 14 LOOP Q(I-1)<=Q(I); A(I)<=Q(I) AND B(I); C(I)<=C(I-1) XOR A(I); END LOOP; OP<=Q(5); WHEN\ C(5) <=Q(5); B(12) <='1'; FOR I IN 6 TO 14 LOOP Q(I-1)<=Q(I);

A(I)<=Q(I) AND B(I); C(I)<=C(I-1) XOR A(I); END LOOP; OP<=Q(5); WHEN\ C(6) <=Q(6); B(10) <='1'; FOR I IN 7 TO 14 LOOP Q(I-1)<=Q(I); A(I)<=Q(I) AND B(I); C(I)<=C(I-1) XOR A(I); END LOOP; OP<=Q(6); WHEN\ C(6) <=Q(6); B(11) <='1'; FOR I IN 7 TO 14 LOOP Q(I-1)<=Q(I); A(I)<=Q(I) AND B(I); C(I)<=C(I-1) XOR A(I); END LOOP; OP<=Q(6); WHEN\ C(7) <=Q(7); B(9) <='1'; B(10) <='1'; B(11) <='1'; FOR I IN 8 TO 14 LOOP Q(I-1)<=Q(I); A(I)<=Q(I) AND B(I); C(I)<=C(I-1) XOR A(I); END LOOP; OP<=Q(7); WHEN\ C(7) <=Q(7); B(11) <='1'; B(12) <='1'; B(13) <='1'; FOR I IN 8 TO 14 LOOP Q(I-1)<=Q(I); A(I)<=Q(I) AND B(I); C(I)<=C(I-1) XOR A(I); END LOOP; OP<=Q(7); WHEN\ C(8) <=Q(8);

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