BY25Q80A_v2.3 博雅小封装spi flash

Boya Microelectronics

Memory Series

BY25Q80A

8M BIT SPI NOR FLASH

Features

● Serial Peripheral Interface (SPI)

- Standard SPI: SCLK, /CS, SI, SO, /WP, /HOLD - Dual SPI: SCLK, /CS, IO0, IO1, /WP, /HOLD - Quad SPI: SCLK, /CS, IO0, IO1, IO2, IO3 ● Read

- Normal Read (Serial): 50MHz clock rate - Fast Read (Serial): 108MHz clock rate

- Dual/Quad (Multi-I/O) Read: 108MHz clock rate

● Program SOP8 150-mil - Serial-input Page Program up to 256bytes - Program Suspend and Resume ● Erase - Block erase (64/32 KB) - Sector erase (4 KB) - Chip erase

- Erase Suspend and Resume

● Program/Erase Speed

- Page Program time: 0.7ms typical SOP8 208-mil - Sector Erase time: 60ms typical - Block Erase time: 0.2/0.4s typical - Chip Erase time: 7s typical ● Flexible Architecture - Sector of 4K-byte

- Block of 32/64K-byte ● Low Power Consumption

- 20mA maximum active current - 5uA maximum power down current

● Software/Hardware Write Protection USON8 3*3 mm - 3x256-Byte Security Registers with OTP Lock - Enable/Disable protection with WP Pin

- Write protect all/portion of memory via software - Top or Bottom, Sector or Block selection ● Single Supply Voltage

- Full voltage range: 2.7~3.6V ● Temperature Range - Commercial (0℃ to +70℃)

- Industrial (-40℃ to +85℃) WSON 6*5 mm ● Cycling Endurance/Data Retention

- Typical 100k Program-Erase cycles on any sector - Typical 20-year data retention at +55℃

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Contents BY25Q80A

Contents

1. Description ....................................................................................................................... 4 2. Signal Description ............................................................................................................ 6

2.1 Input/Output Summary ................................................................................................... 6 2.2 Chip Select (/CS) ............................................................................................................ 6 2.3 Serial Clock (SCLK)....................................................................................................... 6 2.4 Serial Input (SI)/IO0 ....................................................................................................... 7 2.5 Serial Data Output (SO)/IO1 .......................................................................................... 7 2.6 Write Protect (/WP)/IO2 ................................................................................................. 7 2.7 HOLD (/HOLD)/IO3 ...................................................................................................... 7 2.8 VCC Power Supply......................................................................................................... 8 2.9 VSS Ground .................................................................................................................... 8 3. Block/Sector Addresses ................................................................................................... 9 4. SPI Operation ................................................................................................................. 10

4.1 Standard SPI Instructions ............................................................................................. 10 4.2 Dual SPI Instructions .................................................................................................... 10 4.3 Quad SPI Instructions ................................................................................................... 10 5. Operation Features ........................................................................................................ 10

5.1 Supply Voltage .............................................................................................................. 10

5.1.1 Operating Supply Voltage ............................................................................... 10 5.1.2 Power-up Conditions ........................................................................................ 11 5.1.3 Device Reset ..................................................................................................... 11 5.1.4 Power-down ...................................................................................................... 11 5.2 Active Power and Standby Power Modes ..................................................................... 11 5.3 Hold Condition ............................................................................................................. 11 5.4 Status Register .............................................................................................................. 12

5.4.1 Status Register Table ....................................................................................... 12 5.4.2 The Status and Control Bits ............................................................................ 13 5.4.3 Status Register Protect Table ......................................................................... 15 5.4.4 Write Protect Features ..................................................................................... 16 5.4.5 Status Register Memory Protection ............................................................... 16

6. Device Identification ....................................................................................................... 18 7. Instructions Description .................................................................................................. 19

7.1 Configuration and Status Instructions ........................................................................... 22

7.1.1 Write Enable (06H) ........................................................................................... 22 7.1.2 Write Disable (04H) .......................................................................................... 22 7.1.3 Read Status Register (05H or 35H) ............................................................... 23 7.1.4 Write Status Register (01H) ............................................................................ 23 7.1.5 Write Enable for Volatile Status Register (50H) ........................................... 24 7.2 Read Instructions .......................................................................................................... 25

7.2.1 Read Data (03H) .............................................................................................. 25 7.2.2 Fast Read (0BH) ............................................................................................... 26 7.2.3 Dual Output Fast Read (3BH) ........................................................................ 27 7.2.4 Quad Output Fast Read (6BH) ....................................................................... 28 7.2.5 Dual I/O Fast Read (BBH)............................................................................... 29 7.2.6 Dual I/O Fast Read with “Continuous Read Mode” ..................................... 30 7.2.7 Quad I/O Fast Read (EBH) ............................................................................. 31 7.2.8 Quad I/O Fast Read with “Continuous Read Mode” ................................... 32 7.2.9 Continuous Read Mode Reset (FFH or FFFFH) ......................................... 33 7.2.10 Fast Read Quad I/O with “8/16/32/64-Byte Wrap Around” ........................ 34

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Contents BY25Q80A

ID and Security Instructions ......................................................................................... 36 7.3.1 Read Manufacture ID/ Device ID (90H) ........................................................ 36 7.3.2 JEDEC ID (9FH) ............................................................................................... 37 7.3.3 Deep Power-Down (B9H) ................................................................................ 38 7.3.4 Release from Deep Power-Down/Read Device ID (ABH) ......................... 39 7.3.5 Read Security Registers (48H)....................................................................... 40 7.3.6 Erase Security Registers (44H) ...................................................................... 41 7.3.7 Program Security Registers (42H) ................................................................. 42 7.4 Program and Erase Instructions .................................................................................... 43

7.4.1 Page Program (02H) ........................................................................................ 43 7.4.2 Sector Erase (20H) .......................................................................................... 44 7.4.3 32KB Block Erase (52H) ................................................................................. 45 7.4.4 64KB Block Erase (D8H) ................................................................................. 46 7.4.5 Chip Erase (60/C7H) ........................................................................................ 47 7.4.6 Erase / Program Suspend (75H) .................................................................... 48 7.4.7 Erase / Program Resume (7AH) .................................................................... 49 7.5 Reset Device Instructions ............................................................................................. 50

7.5.1 Enable Reset (7Eh) and Reset Device (99h) ............................................... 50 Electrical Characteristics ................................................................................................ 51 8.1 Absolute Maximum Ratings ......................................................................................... 51 8.2 Operating Ranges.......................................................................................................... 51 8.3 Data Retention and Endurance ..................................................................................... 51 8.4 Latch Up Characteristics ............................................................................................... 52 8.5 Power-up Timing .......................................................................................................... 52 8.6 DC Electrical Characteristics ........................................................................................ 53 8.7 AC Measurement Conditions ....................................................................................... 54 8.8 AC Electrical Characteristics ........................................................................................ 54 Package Information ...................................................................................................... 57 9.1 Package 8-Pin SOP 150-mil.......................................................................................... 57 9.2 Package 8-Pin SOP 208-mil.......................................................................................... 58 9.3 Package USON8 (3*3mm) ........................................................................................... 59 9.4 Package WSON8 (6*5mm) .......................................................................................... 60 9.5 Package 8-Pin DIP8L ................................................................................................... 61 Order Information ........................................................................................................... 62 Document Change History ............................................................................................. 63 7.3

8.

9.

10. 11.

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BY25Q80A Description

1. Description

The BY25Q80A is 8M-bit Serial Peripheral Interface(SPI) Flash memory, and supports the Dual/Quad SPI: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2 (/WP), and I/O3 (/HOLD). The Dual I/O data is transferred with speed of 216Mbits/s and the Quad I/O & Quad output data is transferred with speed of 432Mbits/s. The device uses a single low voltage power supply, ranging from 2.7 Volt to 3.6 Volt.

Additionally, the device supports JEDEC standard manufacturer and device ID and three 256-bytes Security Registers.

In order to meet environmental requirements, Boya Microelectronics offers an 8-pin SOP 150-mil, 173-mil or 208mil, an 8-pad WSON 6x5-mm, an 8-pin USON 3x3-mm, and other special order packages, please contacts Boya Microelectronics for ordering information. Figure 1. Logic diagram

VCCSCLKSI/CS/WP/HOLDSOBY25QXXVSS

Figure 2. Pin Configuration SOP 150/208 mil, TSSOP173mil

Top View/CSSO/WP VSS1287SOP8 150/208milTSSOP 173mil65VCC/HOLDSCLKSI34

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BY25Q80A Description

Figure 3. Pin Configuration DIP8L

Top View/CSSO/WP VSS128765VCC/HOLDSCLKSI

34

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SPI Operation BY25Q80A

5.1.2 Power-up Conditions

When the power supply is turned on, VCC rises continuously from VSS to VCC. During this time, the Chip Select (/CS) line is not allowed to float but should follow the VCC voltage, it is therefore recommended to connect the /CS line to VCC via a suitable pull-up resistor.

In addition, the Chip Select (/CS) input offers a built-in safety feature, as the /CS input is edge sensitive as well as level sensitive: after power-up, the device does not become selected until a falling edge has first been detected on Chip Select (/CS). This ensures that Chip Select (/CS) must have been High, prior to going Low to start the first operation. 5.1.3 Device Reset

In order to prevent inadvertent Write operations during power-up (continuous rise of VCC), a power on reset (POR) circuit is included. At Power-up, the device does not respond to any instruction until VCC has reached the power on reset threshold voltage (this threshold is lower than the minimum VCC operating voltage defined in operating ranges of page 51). When VCC has passed the POR threshold, the device is reset. 5.1.4 Power-down

At Power-down (continuous decrease in VCC), as soon as VCC drops from the normal operating voltage to below the power on reset threshold voltage, the device stops responding to any instruction sent to it. During Power-down, the device must be deselected (Chip Select (/CS) should be allowed to follow the voltage applied on VCC) and in Standby Power mode (that is there should be no internal Write cycle in progress).

5.2 Active Power and Standby Power Modes

When Chip Select (/CS) is Low, the device is selected, and in the Active Power mode. The device consumes ICC.

When Chip Select (/CS) is High, the device is deselected. If a Write cycle is not currently in progress, the device then goes in to the Standby Power mode, and the device consumption drops to ICC1.

5.3 Hold Condition

The Hold (/HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence. During the Hold condition, the Serial Data Output (SO) is high impedance, and Serial Data Input (SI) and Serial Clock (SCLK) are Don’t Care. To enter the Hold condition, the device must be selected, with Chip Select (/CS) Low. Normally, the device is kept selected, for the whole duration of the Hold condition. Deselecting the device while it is in the Hold condition, has the effect of resetting the state of the device, and this mechanism can be used if it is required to reset any processes that had been in progress.

The Hold condition starts when the Hold (/HOLD) signal is driven Low at the same time as Serial Clock (SCLK) already being Low (as shown in Figure 4).

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SPI Operation BY25Q80A

The Hold condition ends when the Hold (HOLD) signal is driven High at the same time as Serial Clock (C) already being Low. Figure 4 also shows what happens if the rising and falling edges are not timed to coincide with Serial Clock (SCLK) being Low. Figure 4. Hold condition activation

/CSSCLK/HOLDHOLDHOLD

5.4 Status Register

5.4.1 Status Register Table

See Table 3 and Table 4 for detail description of the Status Register bits. Status Register-2 (SR2) and Status Register-1 (SR1) can be used to provide status on the availability of the Flash memory array, if the device is write enabled or disabled the state of write protection, Quad SPI setting, Security Register lock status, and Erase/Program Suspend status. Table 3. Status Register-2 (SR2) BIT 7 6 5 4 3 2 1 Name SUS Function Default Value 0 0 0 0 0 0 0 Description 0 = Erase/Program not suspended 1 = Erase/Program suspended 0 = Normal Protection Map 1 = Inverted Protection Map OTP Lock Bits 3:1 for Security Registers 3:1 0 = Security Register not protected 1 = Security Register protected Suspend Status Complement CMP Protect LB3 Security LB2 Register Lock Bits LB1 Reserved Reserved QE Quad Enable Status Resister Protect 1 0 = Quad Mode Not Enabled, the /WP pin and /HOLD are enabled. 1 = Quad Mode Enabled, the IO2 and IO3 pins are enabled, and /WP and /HOLD functions are disabled 0 = SRP0 selects whether /WP input has effect on protection of the status register 1 = SRP0 selects Power Supply Lock Down or OTP Lock Down mode 0 SRP1 0

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SPI Operation BY25Q80A

Table 4. Status Register-1 (SR1) BIT 7 6 5 4 3 2 1 Name SRP0 SEC TB BP2 BP1 BP0 WEL Default Value 0 0 0 0 0 0 0 Description 0 = /WP input has no effect or Power Supply Lock Down mode 1 = /WP input can protect the Status Register or OTP Lock Down 0 = BP2-BP0 protect 64KB blocks 1 = BP2-BP0 protect 4KB sectors 0 = BP2-BP0 protect from the Top down 1 = BP2-BP0 protect from the Bottom up 000b = No protection See Table 6 and Table 7 for protection ranges 0 = Not Write Enabled, no embedded operation can start 1 = Write Enabled, embedded operation can start 0 = Not Busy, no embedded operation in progress 1 = Busy, embedded operation in progress Function Status Resister Protect 0 Sector/Block Protect Top/Bottom Protect Block Protect Bits Write Enable Latch Write in Progress Status 0 WIP 0

5.4.2 The Status and Control Bits 5.4.2.1 WIP bit

The Write in Progress (WIP) bit indicates whether the memory is busy in program/erase/write status register progress. When WIP bit sets to 1, means the device is busy in program/erase/write status register progress, when WIP bit sets 0, means the device is not in program/erase/write status register progress. 5.4.2.2 WEL bit

The Write Enable Latch bit indicates the status of the internal Write Enable Latch. When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program or Erase instruction is accepted. 5.4.2.3 SEC, TB, BP2, BP1, BP0 bits

The Block Protect (SEC, TB, BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Program and Erase instructions. These bits are written with the Write Status Register instruction. When the Block Protect (SEC, TB, BP2, BP1, BP0) bits are set to 1, the relevant memory area (as defined in Table 6 and Table 7).becomes protected against Page Program, Sector Erase and Block Erase instructions. The Block Protect (SEC, TB, BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set.

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SPI Operation BY25Q80A

5.4.2.4 SRP1, SRP0 bits

The Status Register Protect (SRP1 and SRP0) bits are non-volatile Read/Write bits in the status register. The SRP bits control the method of write protection: software protection, hardware protection, power supply lock-down or one time programmable protection. 5.4.2.5 QE bit

The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad operation. When the QE bit is set to 0 (Default) the /WP pin and /HOLD pin are enable. When the QE pin is set to 1, the Quad IO2 and IO3 pins are enabled. (The QE bit should never be set to 1 during standard SPI or Dual SPI operation if the /WP or /HOLD pins directly to the power supply or ground).

5.4.2.6 LB3/LB2/LB1 bit

The LB bit is a non-volatile One Time Program (OTP) bit in Status Register that provide the write protect control and status to the Security Registers. The default state of LB is 0, the security registers are unlocked. LB can be set to 1 individually using the Write Register instruction. LB is One Time Programmable, once it’s set to 1, the 256byte Security Registers will become read-only permanently, LB3/2/1 for Security Registers 3:1. 5.4.2.7 CMP bit

The CMP bit is a non-volatile Read/Write bit in the Status Register2 (bit6). It is used in conjunction the SEC-BP0 bits to provide more flexibility for the array protection. Please see the Status registers Memory Protection table for details. The default setting is CMP=0. 5.4.2.8 SUS bit

The SUS bit is a read only bit in the status register2 (bit7) that is set to 1 after executing an Erase/Program Suspend (75H) instruction. The SUS bit is cleared to 0 by Erase/Program Resume (7AH) instruction as well as a power-down, power-up cycle.

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SPI Operation BY25Q80A

5.4.3 Status Register Protect Table Table 5. Status Register protect table SRP1 SRP0 /WP Status Register Software 0 0 X Protected Hardware 0 1 0 Protected Hardware 0 1 1 Unprotected 1 1 0 1 X X Power Supply Lock-Down(1) One Time Program (2) Description The Status Register can be written to after a Write Enable instruction, WEL=1.(Factory Default) /WP=0, the Status Register locked and cannot be written. /WP=1, the Status Register is unlocked and can be written to after a Write Enable instruction, WEL=1. Status Register is protected and cannot be written to again until the next Power-Down, Power-Up cycle. Status Register is permanently protected and cannot be written to. Notes:

1. When SRP1, SRP0= (1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to

(0, 0) state.

2. The One time Program feature is available upon special order. Please contact Boya

Microelectronics for details.

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SPI Operation BY25Q80A

5.4.4 Write Protect Features

1. Software Protection: The Block Protect (SEC, TB, BP2, BP1, BP0) bits define the section of

the memory array that can be read but not change.

2. Hardware Protection: /WP going low to protected the BP0~SEC bits and SRP0~1 bits. 3. Deep Power-Down: In Deep Power-Down Mode, all instructions are ignored except the

Release from deep Power-Down Mode instruction.

4. Write Enable: The Write Enable Latch (WEL) bit must be set prior to every Page Program,

Sector Erase, Block Erase, Chip Erase, Write Status Register and Erase/Program Security Registers instruction.

5.4.5 Status Register Memory Protection 5.4.5.1 Protect Table

Table 6. BY25Q80A Status Register Memory Protection (CMP=0) Status Register Content SEC TB BP2 BP1 BP0 Blocks X 0 0 0 0 0 0 0 0 0 X 1 1 1 1 1 1 1 1 X 0 0 0 0 1 1 1 1 X X 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 0 1 1 1 0 0 0 1 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 0 1 1 0 0 1 1 0 0 NONE 1 15 0 14 to 15 1 12 to 15 0 8 to 15 1 0 0 0 to 1 1 0 to 3 0 0 to 7 1 0 to 15 X 0 to 15 1 15 0 15 1 15 X 15 1 0 0 0 1 0 X 0 Memory Content Addresses NONE 0F0000H-0FFFFFH 0E0000H-0FFFFFH 0C0000H-0FFFFFH 080000H-0FFFFFH 000000H-00FFFFH 000000H-01FFFFH 000000H-03FFFFH 000000H-07FFFFH 000000H-0FFFFFH 000000H-0FFFFFH 0FF000H-0FFFFFH 0FE000H-0FFFFFH 0FC000H-0FFFFFH 0F8000H-0FFFFFH 000000H-000FFFH 000000H-001FFFH 000000H-003FFFH 000000H-007FFFH Density NONE 64KB 128KB 256KB 512KB 64KB 128KB 256KB 512KB 1MB 1MB 4KB 8KB 16KB 32KB 4KB 8KB 16KB 32KB Portion NONE Upper 1/16 Upper 1/8 Upper 1/4 Upper 1/2 Lower 1/16 Lower 1/8 Lower 1/4 Lower 1/2 ALL ALL Top Block Top Block Top Block Top Block Bottom Block Bottom Block Bottom Block Bottom Block

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SPI Operation BY25Q80A

Table 7. BY25Q80A Status Register Memory Protection (CMP=1) Status Register Content SEC TB BP2 BP1 BP0 Blocks X 0 0 0 0 0 0 0 0 0 X 1 1 1 1 1 1 1 1 X 0 0 0 0 1 1 1 1 X X 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 0 1 1 1 0 0 0 1 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 X 1 0 1 X 1 0 1 X 0 to 15 0 to 14 0 to 13 0 to 11 0 to 7 1 to 15 2 to 15 4 to 15 8 to 15 NONE NONE 0 to 15 0 to 15 0 to 15 0 to 15 0 to 15 0 to 15 0 to 15 0 to 15 Memory Content Addresses 000000H-0FFFFFH 000000H-0EFFFFH 000000H-0DFFFFH 000000H-0BFFFFH 000000H-07FFFFH 010000H-0FFFFFH 020000H-0FFFFFH 040000H-0FFFFFH 080000H-0FFFFFH NONE NONE 000000H-0FEFFFH 000000H-0FDFFFH 000000H-0FBFFFH 000000H-0F7FFFH 001000H-0FFFFFH 002000H-0FFFFFH 004000H-0FFFFFH 008000H-0FFFFFH Density 1MB 960KB 896KB 768KB 512KB 960KB 896KB 768KB 512KB NONE NONE 1020KB 1016KB 1008KB 992KB Portion ALL Lower 15/16 Lower 17/8 Lower 3/4 Lower 1/2 Upper 15/16 Upper 7/8 Upper 3/4 Upper 1/2 NONE NONE L - 255/256 L - 127/128 L - 63/64 L - 31/32 1020KB U - 255/256 1016KB U - 127/128 1008KB 992KB U - 63/64 U - 31/32

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Device Identification BY25Q80A

6. Device Identification

Three legacy Instructions are supported to access device identification that can indicate the manufacturer, device type, and capacity (density). The returned data bytes provide the information as shown in the below table.

Table 8. BY25Q80A ID Definition table

Operation Code 9FH 90H ABH M7-M0 E0 E0 ID15-ID8 40 ID7-ID0 14 13 13

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Instructions Description BY25Q80A

7. Instructions Description

All instructions, addresses and data are shifted in and out of the device, beginning with the most significant bit on the first rising edge of SCLK after /CS is driven low. Then, the one byte instruction code must be shifted in to the device, most significant bit first on SI, each bit being latched on the rising edges of SCLK.

See Table 9, every instruction sequence starts with a one-byte instruction code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or none. /CS must be driven high after the last bit of the instruction sequence has been shifted in. For the instruction of Read, Fast Read, Read Status Register or Release from Deep Power Down, and Read Device ID, the shifted-in instruction sequence is followed by a data out sequence. /CS can be driven high after any bit of the data-out sequence is being shifted out.

For the instruction of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write Enable, Write Disable or Deep Power-Down instruction, /CS must be driven high exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. That is /CS must driven high when the number of clock pulses after /CS being driven low is an exact multiple of eight. For Page Program, if at any time the input byte is not a full byte, nothing will happen and WEL will not be reset.

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Instructions Description BY25Q80A

Table 9. Instruction Set Table Instruction Name Byte 1 Write Enable 06H Write Disable 04H Read Status 05H Register-1 Read Status 35H Register-2 Write Enable for Volatile Status 50H Register Write Status Register 01H Read Data 03H Fast Read 0BH Dual Output Fast 3BH Read Dual I/O Fast Read Quad Output Fast Read Quad I/O Fast Read Set Burst with Wrap Continuous Read Reset Page Program Sector Erase Block Erase(32K) Block Erase(64K) Chip Erase Program/Erase Suspend Program/Erase Resume Deep Power-Down Release From Deep Power-Down, And Read Device ID Release From Deep Power-Down Manufacturer/ Device ID JEDEC ID Erase Security Registers(6) Program Security Registers(6) BBH 6BH EBH 77h FFH 02H 20H 52H D8H C7/60H 75H 7AH B9H ABH ABH 90H 9FH 44H 42H Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 (S7-S0) (S15-S8) (S15-S8) A15-A8 A15-A8 A15-A8 A7-A0 M7-M0(2) A15-A8 dummy dummy A7-A0 A7-A0 A7-A0 (D7-D0)(1) A7-A0 (D7-D0)(5) dummy (D7-D0) dummy dummy Next byte (D7-D0) (D7-D0)(1) (S7-S0) A23-A16 A23-A16 A23-A16 A23-A8(2) A23-A16 A23-A0 M7-M0(4) dummy FFH A23-A16 A23-A16 A23-A16 A23-A16 dummy (D7-D0)(3) A15-A8 A15-A8 A15-A8 A15-A8 A7-A0 A7-A0 A7-A0 A7-A0 W8-W0 (D7-D0) Next byte dummy dummy dummy (ID7-ID0) dummy (M7-M0) A23-A16 A23-A16 dummy (ID15-ID8) A15-A8 A15-A8 00H (ID7-ID0) A7-A0 A7-A0 (M7-M0) (ID7-ID0) (D7-D0) (D7-D0)

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Instructions Description BY25Q80A

Read Security Registers(6) Enable Reset Reset Device 48H 7Eh 99h A23-A16 A15-A8 A7-A0 dummy (D7-D0) Notes:

1. Dual Output data

IO0 = (D6, D4, D2, D0) IO1 = (D7, D5, D3, D1)

2. Dual Input Address

IO0 = A22, A20, A18, A16, A14, A12, A10, A8, A6, A4, A2, A0, M6, M4, M2, M0 IO1 = A23, A21, A19, A17, A15, A13, A11, A9, A7, A5, A3, A1, M7, M5, M3

3. Quad Output Data

IO0 = (D4, D0,…..) IO1 = (D5, D1,…..) IO2 = (D6, D2,…..) IO3 = (D7, D3,…..)

4. Quad Input Address

IO0 = A20, A16, A12, A8, A4, A0, M4, M0 IO1 = A21, A17, A13, A9, A5, A1, M5, M1 IO2 = A22, A18, A14, A10, A6, A2, M6, M2 IO3 = A23, A19, A15, A11, A7, A3, M7, M3

5. Fast Read Quad I/O Data

IO0 = (x, x, x, x, D4, D0,…) IO1 = (x, x, x, x, D5, D1,…) IO2 = (x, x, x, x, D6, D2,…) IO3 = (x, x, x, x, D7, D3,…)

6. Security Registers Address:

Security Register0: A23-A16=00h, A15-A8=00h, A7-A0= Byte Address; Security Register1: A23-A16=00h, A15-A8=01h, A7-A0= Byte Address; Security Register2: A23-A16=00h, A15-A8=02h, A7-A0= Byte Address; Security Register3: A23-A16=00h, A15-A8=03h, A7-A0= Byte Address;

Security Register 0 can be used to store the Flash Discoverable Parameters,

The feature is upon special order, please contact Boya Microelectronics for

details.

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Instructions Description BY25Q80A 7.1 Configuration and Status Instructions

7.1.1 Write Enable (06H)

See Figure 5, the Write Enable instruction is for setting the Write Enable Latch bit. The Write Enable Latch bit must be set prior to every Page Program, Sector Erase, Block Erase, Chip Erase and Write Status Register instruction. The Write Enable instruction sequence: /CS goes low sending the Write Enable instruction /CS goes high. Figure 5. Write Enable Sequence Diagram

/CS0SCLK12345677.1.2 Write Disable (04H)

See Figure 6, the Write Disable instruction is for resetting the Write Enable Latch bit. The Write Disable instruction sequence: /CS goes low Sending the Write Disable instruction /CS goes high. The WEL bit is reset by following condition: Power-up and upon completion of the Write Status Register, Page Program, Sector Erase, Block Erase and Chip Erase instructions. Figure 6. Write Disable Sequence Diagram

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SISO/CS0SCLK12Instruction06HHigh_Z

34567 SISOInstruction04HHigh_Z

Instructions Description BY25Q80A

7.1.3 Read Status Register (05H or 35H)

See Figure 7 the Read Status Register (RDSR) instruction is for reading the Status Register. The Status Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write in Progress (WIP) bit before sending a new instruction to the device. It is also possible to read the Status Register continuously. For instruction code “05H”, the SO will output Status Register bits S7~S0. The instruction code “35H”, the SO will output Status Register bits S15~S8. Figure 7. Read Status Register Sequence Diagram

/CS0SCLKInstructionSI05H or 35HHigh_ZS7-S0 or S15-S8 out 76MSB54321076MSB5S7-S0 or S15-S8 out43210123456789101112131415SO

7.1.4 Write Status Register (01H)

See Figure 8, the Write Status Register instruction allows new values to be written to the Status Register. Before it can be accepted, a Write Enable instruction must previously have been executed. After the Write Enable instruction has been decoded and executed, the device sets the Write Enable Latch (WEL).

The Write Status Register instruction has no effect on S15, S1 and S0 of the Status Register. /CS must be driven high after the eighth or sixteen bit of the data byte has been latched in. If not, the Write Status Register instruction is not executed. If /CS is driven high after eighth bit of the data byte, the CMP and QE and SRP1 bits will be cleared to 0. As soon as /CS is driven high, the self-timed Write Status Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status Register may still be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is completed, the Write Enable Latch is reset. The Write Status Register instruction allows the user to change the values of the Block Protect (SEC, TB, BP2, BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Table 3. The Write Status Register instruction also allows the user to set or reset the Status Register Protect (SRP1 and SRP0) bits in accordance with the Write Protect (/WP) signal. The Status Register Protect (SRP1 and SRP0) bits and Write Protect (/WP) signal allow the device to be put in the Hardware Protected Mode. The Write Status Register instruction is not executed once the Hardware Protected Mode is entered.

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Instructions Description BY25Q80A

Figure 8. Write Status Register Sequence Diagram

/CS0SCLKInstructionSI SO01HHigh_Z 7MSB6Status Register in54321 10 1101514131298 1234567891011121314151617181920212223

7.1.5 Write Enable for Volatile Status Register (50H)

See Figure 9, the non-volatile Status Register bits can also be written to as volatile bits. During power up reset, the non-volatile Status Register bits are copied to a volatile version of the Status Register that is used during device operation. This gives more flexibility to change the system configuration and memory protection schemes quickly without waiting for the typical non-volatile bit write cycles or affecting the endurance of the Status Register non-volatile bits. To write the volatile version of the Status Register bits, the Write Enable for Volatile Status Register (50h) instruction must be issued prior to each Write Status Registers (01h) instruction. Write Enable for Volatile Status Register instruction will not set the Write Enable Latch bit, it is only valid for the next following Write Status Registers instruction, to change the volatile Status Register bit values. Figure 9. Write Enable for Volatile Status Register

/CS0SCLK1234567

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SISOInstruction50HHigh_Z

Instructions Description BY25Q80A 7.2 Read Instructions

7.2.1 Read Data (03H)

See Figure 10, the Read Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being latched-in during the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fR, during the falling edge of SCLK. The address is automatically incremented to the next higher address after each byte of data is shifted out allowing for a continuous stream of data. This means that the entire memory can be accessed with a single command as long as the clock continues. The command is completed by driving /CS high. The whole memory can be read with a single Read Data Bytes (READ) instruction. Any Read Data Bytes (READ) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Normal read mode running up to 50MHz.

Figure 10. Read Data Bytes Sequence Diagram

/CSSCLKSI SO012345678910282930313233343536373839Instruction03HHigh_Z 2322MSB24-Bit Address2132106 5 High_Z2103Data Byte17MSB4

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Instructions Description BY25Q80A

7.2.2 Fast Read (0BH)

See Figure 11, the Read Data Bytes at Higher Speed (Fast Read) instruction is for quickly reading data out. It is followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fc, during the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. Figure 11. Fast Read Sequence Diagram /CS0SCLKInstructionSISO /CSSCLKDummy ClocksSISOHigh_ZData byte 176543210High_ZHigh_Z0BHHigh_Z 32333435363738394041424344454647 232224-Bit Address2132101234567891028293031

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Instructions Description BY25Q80A

7.2.3 Dual Output Fast Read (3BH)

See Figure 12, the Dual Output Fast Read instruction is followed by 3-byte address (A23-A0) and a dummy byte, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out.

Figure 12. Dual Output Fast Read Sequence Diagram

/CS0SCLKInstructionSISO/CS32SCLKSISODummy Clocks6745230167452301High_ZHigh_Z333435363738394041424344454647High_Z 3BH232224-Bit Address2132101234567891028293031 High_ZData Byte 1Data Byte 2

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Instructions Description BY25Q80A

7.2.4 Quad Output Fast Read (6BH)

See Figure 13, the Quad Output Fast Read instruction is followed by 3-byte address (A23-A0) and a dummy byte, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO3, IO2, IO1 and IO0. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out.

Figure 13. Quad Output Fast Read Sequence Diagram

/CS0SCLKInstructionSI(IO0)SO(IO1)/WP(IO2)/HOLD(IO3)/CSSCLKSI(IO0)SO(IO1)/WP(IO2)/HOLD(IO3)Dummy Clocks4High_Z0404040High_Z323334356BHHigh_ZHigh_ZHigh_Z23222124-Bit Address32101234567891028293031 36373839404142434445464751515151High_ZHigh_Z62626262High_ZHigh_Z73Byte173Byte273Byte337Byte4High_Z

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Instructions Description BY25Q80A

7.2.5 Dual I/O Fast Read (BBH)

See Figure 14, the Dual I/O Fast Read instruction is similar to the Dual Output Fast Read instruction but with the capability to input the 3-byte address (A23-0) and a “Continuous Read Mode” byte 2-bit per clock by SI and SO, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out.

Figure 14. Dual I/O Fast Read Sequence Diagram (Initial command or previous M5-4≠10)

/CS0SCLKInstructionSI(IO0)SO(IO1)BBHHigh_Z642064206420642012345678910111213141516171819202122237531753175317531A23-16/CSSCLKSI(IO0)SO(IO1)2324252627282930313233A15-8A7-0M7-03435363738396420642064206420High_Z7531753175317

Byte 1Byte 2 Byte 335Byte 41High_Z

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Instructions Description BY25Q80A

7.2.6 Dual I/O Fast Read with “Continuous Read Mode”

The Fast Read Dual I/O command can further reduce instruction overhead through setting the “Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in Figure 14. The upper nibble of the (M7-4) controls the length of the next Fast Read Dual I/O command through the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t care (“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock. If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Dual I/O command (after /CS is raised and then lowered) does not require the BBH instruction code, as shown in Figure 15. This reduces the command sequence by eight clocks and allows the Read address to be immediately entered after /CS is asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next command (after /CS is raised and then lowered) requires the first byte instruction code, thus returning to normal operation. A “Continuous Read Mode” Reset command can also be used to reset (M7-0) before issuing normal commands (see Continuous Read Mode Reset (FFH or FFFFH)).

Figure 15. Dual I/O Fast Read Sequence Diagram (Previous command set M5-4 =10)

/CSSCLKSI(IO0)SO(IO1)/CSSCLKSI(IO0) SO(IO1)06714223046754627086791011121314154201674201531A23-16531A15-853A7-053M7-015161718192021222324252627282930316742016742672014201046753Byte1531Byte253Byte353Byte4

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Instructions Description BY25Q80A

7.2.7 Quad I/O Fast Read (EBH)

See Figure 16, the Quad I/O Fast Read instruction is similar to the Dual I/O Fast Read instruction but with the capability to input the 3-byte address (A23-0) and a “Continuous Read Mode” byte and 4-dummy clock 4-bit per clock by IO0, IO1, IO3, IO4, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO0, IO1, IO2, IO3. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The Quad Enable bit (QE) of Status Register must be set to enable for the Quad I/O Fast read instruction.

Figure 16. Quad I/O Fast Read Sequence Diagram (Initial command or previous M5-4≠10)

/CS0SCLKSI(IO0)SO(IO1)/WP(IO2)/HOLD(IO3)InstructionEBHHigh_ZHigh_ZHigh_Z45601245601245601245670123Dummy456012456012123456789 10111213141516171819202122237373A23-16A15-873A7-073Byte173Byte2

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Instructions Description BY25Q80A

7.2.8 Quad I/O Fast Read with “Continuous Read Mode”

The Fast Read Quad I/O command can further reduce instruction overhead through setting the “Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in Figure 16, The upper nibble of the (M7-4) controls the length of the next Fast Read Quad I/O command through the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t care (“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock. If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Quad I/O command (after /CS is raised and then lowered) does not require the EBH instruction code, as shown in Figure 17, This reduces the command sequence by eight clocks and allows the Read address to be immediately entered after /CS is asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next command (after /CS is raised and then lowered) requires the first byte instruction code, thus returning to normal operation. A “Continuous Read Mode” Reset command can also be used to reset (M7-0) before issuing normal commands (see Continuous Read Mode Reset (FFH or FFFFH)).

Figure 17. Quad I/O Fast Read Sequence Diagram (Previous command set M5-4 =10)

/CS0SCLKSI(IO0)SO(IO1)/WP(IO2)/HOLD(IO3)45670123124567012334456750123456760123789101112131415456012456012A23-16A15-8A7-0M7-0Dummy73Byte173Byte2

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Instructions Description BY25Q80A

7.2.9 Continuous Read Mode Reset (FFH or FFFFH)

The “Continuous Read Mode” bits are used in conjunction with “Fast Read Dual I/O” and “Fast Read Quad I/O” Instructions to provide the highest random Flash memory access rate with minimum SPI instruction overhead, thus allowing more efficient XIP (execute in place) with this device family.

The “Continuous Read Mode” bits M7-0 are set by the Dual/Quad I/O Read Instructions. M5-4 are used to control whether the 8-bit SPI instruction code (BBh or EBh) is needed or not for the next instruction. When M5-4 = (1,0), the next instruction will be treated the same as the current Dual/Quad I/O Read instruction without needing the 8-bit instruction code; when M5-4 do not equal to (1,0), the device returns to normal SPI instruction mode, in which all instructions can be accepted. M7-6 and M3-0 are reserved bits for future use, either 0 or 1 values can be used. See Figure 18, the Continuous Read Mode Reset instruction (FFh or FFFFh) can be used to set M4 = 1, thus the device will release the Continuous Read Mode and return to normal SPI operation.

To reset “Continuous Read Mode” during Quad I/O operation, only eight clocks are needed. The instruction is “FFh”. To reset “Continuous Read Mode” during Dual I/O operation, sixteen clocks are needed to shift in instruction “FFFFh

Figure 18. Continuous Read Mode Reset Sequence Diagram

/CS0SCLKSI(IO0)SO(IO1)/WP(IO2)/HOLD(IO3)123456789101112131415InstructionFFHDon’t CareDon’t CareDon’t CareFFFFH

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Instructions Description BY25Q80A

7.2.10 Fast Read Quad I/O with “8/16/32/64-Byte Wrap Around”

The Fast Read Quad I/O instruction can also be used to access a specific portion within a page by issuing a “Set Burst with Wrap” (77h) instruction prior to EBh. The “Set Burst with Wrap” (77h) instruction can either enable or disable the “Wrap Around” feature for the following EBh instructions. When “Wrap Around” is enabled, the data being accessed can be limited to either an 8, 16, 32 or 64-byte section of a 256-byte page. The output data starts at the initial address specified in the instruction, once it reaches the ending boundary of the 8/16/32/64-byte section, the output will wrap around to the beginning boundary automatically until /CS is pulled high to terminate the instruction.

The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read instructions.

The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6-4 to be set. The W4 bit is used to enable or disable the “Wrap Around” operation while W6-5 are used to specify the length of the wrap around section within a page.

Similar to a Quad I/O instruction, the Set Burst with Wrap instruction is initiated by driving the /CS pin low and then shifting the instruction code “77h” followed by 24 dummy bits and 8 “Wrap Bits”, W7-0. Wrap bit W7 and the lower nibble W3-0 are not used.

Once W6-4 is set by a Set Burst with Wrap instruction, all the following “Fast Read Quad I/O” and “Word Read Quad I/O” instructions will use the W6-4 setting to access the 8/16/32/64-byte section within any page. To exit the “Wrap Around” function and return to normal read operation, another Set Burst with Wrap instruction should be issued to set W4=1. The default value of W4 upon power on is 1.

W4 = 0 W6 W5 Wrap Around 0 0 0 1 1 0 1 1 Yes Yes Yes Yes Wrap Length 8-byte 16-byte 32-byte 64-byte Wrap Around No No No No Wrap Length N/A N/A N/A N/A W4 =1 (DEFAULT)

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Instructions Description BY25Q80A

Figure 19. Set Burst with Wrap Command Sequence

/CS0SCLKSI(IO0)Instruction77HHigh_Z123456789101112131415xxxxxxxxxxxxxxxxxxxxxxxxW4xxxxHigh_ZSO(IO1)/WP(IO2)/HOLD(IO3)W5High_ZHigh_ZHigh_ZW6High_ZxHigh_ZByte1Byte2Byte3Byte4

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Instructions Description BY25Q80A 7.3 ID and Security Instructions

7.3.1 Read Manufacture ID/ Device ID (90H)

See Figure 20, the Read Manufacturer/Device ID instruction is an alternative to the Release from Power-Down/Device ID instruction that provides both the JEDEC assigned Manufacturer ID and the specific Device ID.

The instruction is initiated by driving the /CS pin low and shifting the instruction code “90H” followed by a 24-bit address (A23-A0) of 000000H. If the 24-bit address is initially set to 000001H, the Device ID will be read first.

Figure 20. Read Manufacture ID/ Device ID Sequence Diagram /CS0SCLKInstructionSISO/CS3233343536SCLKSISO76Manufacturer ID54321076Device ID325410373839404142434445464790HHigh_Z24-Bit Address32232221101234567891028293031

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Instructions Description BY25Q80A

7.3.2 JEDEC ID (9FH)

The JEDEC ID instruction allows the 8-bit manufacturer identification to be read, followed by two bytes of device identification. The device identification indicates the memory type in the first byte, and the memory capacity of the device in the second byte. JEDEC ID instruction while an Erase or Program cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. The JEDEC ID instruction should not be issued while the device is in Deep Power-Down Mode. See Figure 21, he device is first selected by driving /CS to low. Then, the 8-bit instruction code for the instruction is shifted in. This is followed by the 24-bit device identification, stored in the memory, being shifted out on Serial Data Output, each bit being shifted out during the falling edge of Serial Clock. The JEDEC ID instruction is terminated by driving /CS to high at any time during data output. When /CS is driven high, the device is put in the Standby Mode. Once in the Standby Mode, the device waits to be selected, so that it can receive, decode and execute instructions. Figure 21. JEDEC ID Sequence Diagram

/CSSCLKSISO/CSSCLKSISO7MSB01234567891011121314159FHInstruction7MSB6Manufacturer ID5432101617181920212223242526 2728293031Memory Type ID15-ID865432107MSB

Capacity ID7-ID06543210

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Instructions Description BY25Q80A

7.3.3 Deep Power-Down (B9H)

Although the standby current during normal operation is relatively low, standby current can be further reduced with the Deep Power-down instruction. The lower power consumption makes the Deep Power-down (DPD) instruction especially useful for battery powered applications (see ICC1 and ICC2). The instruction is initiated by driving the /CS pin low and shifting the instruction code “B9h” as shown in Figure 22.

The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Deep Power down instruction will not be executed. After /CS is driven high, the power-down state will entered within the time duration of tDP. While in the power-down state only the Release from Deep Power-down / Device ID instruction, which restores the device to normal operation, will be recognized. All other Instructions are ignored. This includes the Read Status Register instruction, which is always available during normal operation. Ignoring all but one instruction also makes the Power Down state a useful condition for securing maximum write protection. The device always powers-up in the normal operation with the standby current of ICC1. Figure 22. Deep Power-Down Sequence Diagram

/CS0SCLKInstructionSIB9HStand-by modePower-down mode1234567tDP

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Instructions Description BY25Q80A

7.3.4 Release from Deep Power-Down/Read Device ID (ABH)

The Release from Power-Down or Device ID instruction is a multi-purpose instruction. It can be used to release the device from the Power-Down state or obtain the devices electronic identification (ID) number.

See Figure 23a, to release the device from the Power-Down state, the instruction is issued by driving the /CS pin low, shifting the instruction code “ABH” and driving /CS high Release from Power-Down will take the time duration of tRES1 (See AC Characteristics) before the device will resume normal operation and other instruction are accepted. The /CS pin must remain high during the tRES1 time duration.

When used only to obtain the Device ID while not in the Power-Down state, the instruction is initiated by driving the /CS pin low and shifting the instruction code “ABH” followed by 3-dummy byte. The Device ID bits are then shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure 23b. The Device ID value for the BY25Q80A is listed in Manufacturer and Device Identification table. The Device ID can be read continuously. The instruction is completed by driving /CS high.

When used to release the device from the Power-Down state and obtain the Device ID, the instruction is the same as previously described, and shown in Figure 23b, except that after /CS is driven high it must remain high for a time duration of tRES2 (See AC Characteristics). After this time duration the device will resume normal operation and other instruction will be accepted. If the Release from Power-Down/Device ID instruction is issued while an Erase, Program or Write cycle is in process (when WIP equal 1) the instruction is ignored and will not have any effects on the current cycle.

Figure 23a. Release Power-Down Sequence Diagram

/CS0SCLKInstructionSIABHPower-down modeStand-by mode1234567tRES1Figure 23b. Release Power-Down/Read Device ID Sequence Diagram

/CSSCLKInstructionSISOABHHigh_Z3 Dummy Bytes232221MSBtRES2076MSBDevice ID354210Stand-by mode01234567892930313233343536373839Deep Power-down mode

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Instructions Description BY25Q80A

7.3.5 Read Security Registers (48H)

See Figure 24, the Read Security Registers instruction is similar to Fast Read instruction. The instruction is followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fC, during the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. Once the A9-A0 address reaches the last byte of the register (Byte 3FFH), it will reset to 000H, the instruction is completed by driving /CS high.

Address Security Registers 1 Security Registers 2 Security Registers 3 A23-A16 00H 00H 00H A15-A8 01H 02H 03H A7-A0 Byte Address Byte Address Byte Address Figure 24. Read Security Registers instruction Sequence Diagram

/CS0SCLKInstructionSISO/CS32333435363738394041424344454647SCLKDummy ByteSISO76543210Data Byte 11234567892829303124-Bit Address48HHigh_Z2322321076MSB543210

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