PCIe 2.0 3.0验证、调试和一致性测试解决方案

PCIe 2.0 3.0验证、调试和一致性测试解决方案

PCI Express 3.0 Testing Approaches for PHY and Protocol Layersname title

PCIe 2.0 3.0验证、调试和一致性测试解决方案

Agenda Introduction to PCI Express 3.0– Trends and Challenges Physical Layer Testing Overview– – – Transmitter Design & Validation Transmitter Compliance Receiver & Summary of Tools for PCIe PHY Testing Protocol– – – Planning probe access Time to confidence Information density Applications Summary22010-4-26Tektronix Innovation Forum 2010

PCIe 2.0 3.0验证、调试和一致性测试解决方案

PCI Express 3.0 Technology TimelineToday 20090.5 Release 0.7 Release 0.71 Release201020112112Base Spec0.5 Release 0.7 DraftCEM Spec0.3 ReleaseTest SpecDeployment Phase Integration Phase– – Product Development PCI-SIG Tool DevelopmentSilicon Phase–CEM Spec DevelopmentPresentation Content based on .9 Base Specification Draft and .7 CEM Specification DraftTektronix Involved in PCIe EWG, CEM, and Serial Enabling Working Groups3 2010-4-26 Tektronix Innovation Forum 2010

PCIe 2.0 3.0验证、调试和一致性测试解决方案

PCI Express 3.0Trends and ImplicationsIndustry/Technology Trends Data transfer rates continue to increase:2.558 GT/s 128b/130b encoding Backwards interoperability Energy efficiency (Lower mW/Gb/s)Implications Greater system complexity increasesthe engineering challenge Higher data rate signals have lessmargin – requires de-embedding Crosstalk, skew, noise and attenuationmore significant Link training and power managementcontinue to be the most difficult challenges4 2010-4-26 Tektronix Innovation Forum 2010

PCIe 2.0 3.0验证、调试和一致性测试解决方案

High Speed Serial Test ChallengesDesign Verification Compliance TestTransaction LayerSystem IntegrationDigital Validation & DebugData Link AnalysisDigital validation & DebugData Link LayerLogical Sub-blockComplete Validation, Debug, Compliance Solutions!! Receiver Test Simulation Signal IntegrityEye and Jitter Analysis Characterization & Validation Direct SynthesisCompliance TestingPhysical Layer+ -Electrical Sub-blockSerial Data Network & Link AnalysisTx+ + -path+ -Rx52010-4-26Tektronix Innovation Forum 2010

PCIe 2.0 3.0验证、调试和一致性测试解决方案

Agenda Introduction to PCI Express 3.0– Trends and Challenges Physical Layer Testing Overview– – – Transmitter Design & Validation Transmitter Compliance Receiver & Summary of Tools for PCIe PHY Testing Protocol– – – Planning probe access Time to confidence Information density Applications Summary62010-4-26Tektronix Innovation Forum 2010

PCIe 2.0 3.0验证、调试和一致性测试解决方案

What’s New for PCI Express Gen 3.0Double bandwidth (8GT/s with 128b/130b) while using traditional circuit board (FR-4) Requires de-embedding measurements to Tx pins, specifies breakout and replica channels. Large channel losses require Tx and Rx equalization– Tx equalization- Defined pre-shoot and deemphasis Presets – Rx equalization– behavioral CTLE & DFENew jitter separation algorithms72010-4-26Tektronix Innovation Forum 2010

PCIe 2.0 3.0验证、调试和一致性测试解决方案

Transmitter Design & ValidationPCI Express

PCIe 2.0 3.0验证、调试和一致性测试解决方案

PCIe 3.0 Base Spec Transmitter Voltage and Jitter MeasurementsBase Spec Measurements defined at the pins of the transmitter New Jitter Measurements are defined for PCIe 3.092010-4-26Tektronix Innovation Forum 2010

PCIe 2.0 3.0验证、调试和一致性测试解决方案

New PCIe 3.0 Jitter MeasurementsUncorrelated Total Jitter and Uncorrelated Deterministic Jitter– Uncorrelated jitter is not mitigated by Tx or Rx equalization and represents timing margin that cannot be recovered with equalization. – Data Dependent Jitter is determined by averaging from a repeated compliance pattern – Uncorrelated Jitter derived after removing Data Dependent Jitter – Construct the bathtub curve in Q scale – Estimate Total Jitter with Q Scale extrapolation102010-4-26Tektronix Innovation Forum 2010

PCIe 2.0 3.0验证、调试和一致性测试解决方案

New PCIe 3.0 Jitter Measurements (cont’d)Uncorrelated Total and Deterministic PWJ– Long lossy channels cause single pulses to be attenuated – ISI contributions need to be removed to determine PWJ – Calculate the edge to edge Jitter – Construct the bathtub curve in Q scale – Estimate Total Jitter with Q Scale extrapolation112010-4-26Tektronix Innovation Forum 2010

PCIe 2.0 3.0验证、调试和一致性测试解决方案

Transmitter Characterization Tx measurements referenced to pins but can only access TP1 Extract replica channel transfer function (S-Parameter) Acquire signals at TP1 then mathematically remove channel effectsTest Channel.s4p12 2010-4-26 Tektronix Innovation Forum 2010

PCIe 2.0 3.0验证、调试和一致性测试解决方案

De-embeddingRemoval of signal impairment caused by selected known part of the circuit. Measurement setup often known – i.e., a fixture.When impacts does the test fixture add? What does the signal look like at the Tx, without the fixture?+ + - - Fixt ureMeasuredDe-embedded (calculated in oscilloscope from ‘Measure’ and from network parameters of fixture)… close to the ‘True’TrueMeasure the Fixture (with TDR, VNA, etc) and and capture the network’s parameters (e.g. as a S parameter touchstone file) In the oscilloscope Import the S parameter file, view the waveform as it was at the source.2010-4-26 Tektronix Innovation Forum 20101313

PCIe 2.0 3.0验证、调试和一致性测试解决方案

Probing and Signal Access Typically used when a signal needs to be measured and no SMA or RF connector is available Debug– – Require a quick way to check that signals are present Solder tips can be used for a more permanent connection for troubleshooting Validation and Compliance Testing– Chip to chip buses142010-4-26Tektronix Innovation Forum 2010

PCIe 2.0 3.0验证、调试和一致性测试解决方案

Tektronix’ Solutions for PCIe 3.0 Base Spec TestingAvailable Today Channel Embedding / Deembedding support with (Serial Data Link Analysis) Software TX Voltage VTX-FS-NO-EQ and VTXRS-NO-EQ Measurements available today in DPOJET 20Ghz Real-Time Oscilloscope and Probes for Fifth Harmonic CaptureTektronix DPOJET PCIe 3.0 SW152010-4-26Tektronix Innovation Forum 2010

PCIe 2.0 3.0验证、调试和一致性测试解决方案

Transmitter CompliancePCI Express

PCIe 2.0 3.0验证、调试和一致性测试解决方案

CEM Specification Add-In Card Transmitter TestingTX measurements based on one preset value (assumption is the best preset will be used for compliance) Measurements taken after RX Equalization using the Compliance Base Board Voltage Measurements on Both Transition and Non-Transition Bits at a BER of 10-6 Eye Width Measurements taken with a sample of at least 106 UI and Eye opening is computed at 10-6Preset Number P4 P1 P0 P9 P8 P7 P5 P6 P3 P2 P10 preshoot (dB) 0.0 0.0 0.0 3.5 ±1 dB 3.5 ±1 dB 3.5 ±1 dB 1.9 ±1 dB 2.5 ±1 dB 0.0 0.0 0.0 de-emph (dB) 0.0 -3.5 ±1 dB -6.0 ±1.5 dB 0.0 -3.5 ±1 dB -6.0 ±1.5 dB 0.0 0.0 -2.5 ±1 dB -4.4 ±1.5 dB -9.5 ± 1.5 dB c-1 0.000 0.000 0.000 -0.166 -0.125 -0.100 -0.100 -0.125 0.000 0.000 0.000 c +1 0.000 -0.167 -0.250 0.000 -0.125 -0.200 0.000 0.000 -0.125 -0.200 -0.333 Va 1.000 1.000 1.000 0.668 0.750 0.800 0.800 0.750 1.000 1.000 1.000 Vb 1.000 0.668 0.500 0.668 0.500 0.400 0.800 0.750 0.750 0.600 0.333 Vc 1.000 0.668 0.500 1.000 0.750 0.600 1.000 1.000 0.750 0.600 0.333172010-4-26Tektronix Innovation Forum 2010

PCIe 2.0 3.0验证、调试和一致性测试解决方案

CEM Specification System Transmitter TestingSame methodology as Add-In Card Testing, but uses the dual port method (clock and data) Measurements taken after RX Equalization using the Compliance Load Board Voltage Measurements on Both Transition and Non-Transition Bits at a BER of 10-6 Eye Width Measurements taken with a sample of at least 106 UI and Eye opening is computed at 10-6182010-4-26Tektronix Innovation Forum 2010

PCIe 2.0 3.0验证、调试和一致性测试解决方案

Receiver EqualizationPCIe Gen 3.0 uses Transmitter De-emphasis plus RX CTLE and Dfe What would the signal look like inside the receiver after equalization?result after emulated channel+ + - -result after EqualizationMeasured Eye out of TxLink analysis with Continuous Time Linear Equalizer (CTLE) or Decision Feedback (DFE) Equalizers Three DFE modesCoefficients values adapted based on measured dataAuto adapt taps Coefficient values adapted based on existing tapsAdapt from current taps Do not adaptSlicer controls and training sequence support19 2010-4-26 Tektronix Innovation Forum 201019

PCIe 2.0 3.0验证、调试和一致性测试解决方案

Tektronix’ Solutions for PCIe 3.0 CEM TestingAvailable Today Receiver Equalization support for CTLE and DFE with SDLA (Serial Data Link Analysis) Software Measurements available today in DPOJETTektronix DPOJET SWPCI-SIG SigTest SW202010-4-26Tektronix Innovation Forum 2010

PCIe 2.0 3.0验证、调试和一致性测试解决方案

Summary of Tektronix Tools for PCIe TestingTDR/TDT/IConnect for Serial Data Network Analysis50 GHz TDR/TDT system and S-Parameter measurements, highly accurate impedance and loss measurements Up to 1M record lengthReal-Time Oscilloscope and Analysis ToolsTransmitter Validation, Debug, Compliance, and Receiver Calibration “Complete Link” – channel embedding/de-embedding, equalization (CTLE/DFE) with SDLA CEM and Base Spec Measurements with DPOJET and TekExpress TriMode Differential probes – 20GHz to the probe tipReceiver Stress GenerationFlexibility to support all signal impairments required for jitter tolerance testing Model real-world complexities of SSC profiles to avoid system interoperability issues21 2010-4-26 Tektronix Innovation Forum 2010212010年4月26日星期一Tektronix Confidential V0.98

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