WiFiMod_WM-G-MR-09_Application Circuit_20071012

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WM-G-MR-09 Application Circuit WLAN 802.11b/g 8.2mmx8.4mm SiP ModuleBluetooth Coexistence SDIO/G-SPI Interface

Block DiagramD

C

QQ H: tt 41 p: 79// 90 Wi 13 Fi 4 Mo

d.

tk

C

POWER SUPPLY

WM-G-MR-09

WLAN RF port

B

开

发

网

B

Wi Fi

Configuration

OSC 32.768KHz for Sleep CLK

Table of Contents---------------------------------------------------------------------

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1 2 3 4

Blockdiagram Schematic Bluetooth Coexistence Change History

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Design Engineer: Camus Chen

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Title WM-G-MR-09 Application Circuit Size Date:2

Document Number<Doc> Friday, October 12, 2007 Sheet1

Rev 0.2 1 of 4

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4

3

2

1

J1D

External sleep clockANT VDD_HOST_IO C1

D

U1 R1 4 3.3R VDC E/D 1

50 ohm trace

NL R2 0R C4

C2 10uF

C3 1nF3 O/P GND 2

32.768 KHz OSCR3SLEEP_CLK 33R

NL

Firmware Boot ROM selectR4 SCLK

External Reference Circuit for Clock source

SD_DATA_1 SCLK ECSn ECSN R5

tk

R4 (SCLK)

R5 (ECSn)

BOOT from SPI EEPROM

No Load

100K

d.

BOOT from host interface bus

No Load

No Load

C

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C

VDD_HOST_IO

VDD3.3

2

4

5

6

1

3

7

8

U2

SCLK

GND

GND

SD_DAT[1]

ECSn

GND

ANT

Host I/F VoltageR6

VDD_HOST_IO SLEEP_CLK R7 100K GPIO_0 BT_PRIORITY RESETn PDN WL_ACTIVE

36 35 34 33 32 31 30 29 28

NC

PW_SEL SLEEP_CLK GPIO[0] BT_PRIORITY RESETn PDn WL_ACTIVE BT_STATE VDD3.3

VDD_HOST_IO

9

GPIO[6] GPIO[5]

10 11

GPIO_6 GPIO_5

C5 1uF

C6 0.1uFR8

R6 Host I/F Voltage: 3.3V Host I/F Voltage: 1.8V 0R NL

R8 NL 0R

SD_DAT[3]

12

SD_DATA_3 GPIO_2

GPIO[2]

13

SD_CLK

14

SD_CLK GPIO_4 GPIO_1

PowerVDD_3.3: Max Current rating= 300 mA

GPIO[4] GPIO[1] VDD1.8 VDD1.2

15 16

VDD1.8

VDD3.3

BT_STATE

17 18

SD_DAT[2]

IF_SEL_2

IF_SEL_1

GND

GND

C7 4.7uF

C8 2.2uF

VDD3.3

SD_CMD

VDD1.8A

27

SD_DAT[0]

C9 1uF

C10 0.1uF

C11 1uF

C12 0.1uF

26

25

24

23

22

21

20

网

19

WM-G-MR-09 module_footprint

Keep GPIO[5]& GPIO[6] open for internal XTAL 38.4MHzB

B

发开

SD_CMD

SD_DATA_0 SD_DATA_2 IF_SEL_1 IF_SEL_2

WLAN Host Interface selectR9 IF_SEL_1

U3

U4

Wi Fi

Host interface

R9 (IF_SEL_1)

R10 (IF_SEL_2)

SD_DATA_3 SD_DATA_2 SD_DATA_1 SD_DATA_0 SD_CMD SD_CLK

1 2 3 4 5 6 7

SDIO_D3 SDIO_D2 SDIO_D1 SDIO_D0 SDIO_CMD SDIO_CLK GND

SD_DATA_3 SD_DATA_2 SD_DATA_1 SD_DATA_0 SD_CMD SD_CLK

1 2 3 4 5 6 7

G-SPI_CLK_REQ G-SPI_SINTn G-SPI_SDO G-SPI_SCSn G-SPI_SDI G-SPI_CLK GND

C13 0.1uF

C14 1uFR10 IF_SEL_2

SDIO G-SPI

No Load 100K

No Load 100K

SDIO Controller

G-SPI Controller

A

Note: The signal level should be the same as VDD_HOST_IO. (Pin 9 of module)

A

25 4 3 2

Design Engineer: Camus Chen Title WM-G-MR-09 Application Circuit Size Date: Document Number<Doc> Friday, October 12, 20071

Rev 0.2 Sheet 2 of 4

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R11 BT_STATE 10KD

BT_STATE_host

(3.3V referred)D

Level of WL_ACTIVE, BT_STATE and BT_PRIORITY are 1.8V

R12 15K

VDD1.8

VDD3.3

tkST1 ST1G3234

d.

R13 BT_PRIORITY_host 10K R14 15K

QQ H: tt 41 p: 79

// 90 Wi 13 Fi 4 Mo

C3C

VCCB GND B1

VCCA A1

A3 A1

BT_PRIORITY WL_ACTIVE_host

(3.3V referred)C

WL_ACTIVE

C1

(3.3V referred)B2

B

开

发

网

B

A

Wi Fi

A

Design Engineer: Camus Chen Title WM-G-MR-09 Application Circuit Size Date:5 4 3

Document Number<Doc> Friday, October 12, 20072

Rev 0.2 Sheet 31

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1

Change History 20070629: First Release 20070914: U2 pin4 change to NCD

C

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d.

U2 pin9 change to VDD3.3 Remove VDD_HOST_IO, R6, R8 Leave U2 pin4& pin 36 as NC 20070917: Restore R6& R8 20071012: U2 pin9 restore to VDD_HOST_IO Swap ST1G3234 pin A1, A3 and C1, C3 Sleep clock powered by VDD_HOST_IO Add level description for WL_ACTIVE, BT_STATE and BT_PRIORITY

D

tk

C

B

开

发

网

B

A

Wi Fi

Design Engineer: Camus Chen Title WM-G-MR-09 Application Circuit Size Date:5 4 3

A

Document Number<Doc> Friday, October 12, 20072

Rev 0.1 Sheet 41

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