单周期CPU verilog语言

Alu.v

module ALU(aluControl,a,b,result,zero); input[3:0] aluControl; input[31:0] a,b; output zero;

output[31:0] result; reg[31:0] result;

always @(aluControl or a or b) begin

case(aluControl)

4'b0000: result=a&b; 4'b0001: result=a|b; 4'b0010: result=a+b; 4'b0110: result=a-b;

4'b0111: result= (a

assign zero=(result==0) ? 1 : 0;

endmodule

ALUcontrol.v

module ALUcontrol (aluop,funct,aluControl); input [1:0]aluop; input [5:0]funct; output reg[3:0]aluControl; always@(*) begin case (aluop) 2'b00: aluControl<=4'b0010; 2'b01: aluControl<=4'b0110; 2'b10: begin case (funct) 6'b100000: aluControl<=4'b0010; 6'b100010: aluControl<=4'b0110; 6'b100100: aluControl<=4'b0000; 6'b100101: aluControl<=4'b0001; 6'b101010: aluControl<=4'b0111; default : aluControl<=4'b0010;

endcase end default : aluControl<=4'b0010; endcase end endmodule

Ctrl.v

module

controlUnit(instruction,zero,RegDst,Jump,Branch,MemRead,MemtoReg,ALUOp,MemWrite,ALUsrc,RegWrite); input [5:0]instruction; input zero; output reg RegDst; output reg Jump; output reg Branch; output reg MemRead; output reg MemtoReg; output reg[1:0]ALUOp; output reg MemWrite; output reg ALUsrc; output reg RegWrite; always@(*) begin case (instruction) 6'b000000://R type begin RegDst=1; ALUsrc=0; MemtoReg=0; RegWrite=1; MemRead=0; MemWrite=0; Branch=0; ALUOp[1]=1; ALUOp[0]=0; Jump=1; end 6'b001000://addi

begin RegDst=0; ALUsrc=1; MemtoReg=0; RegWrite=1; MemRead=0; MemWrite=0; Branch=0; ALUOp[1]=1; ALUOp[0]=0; Jump=1; end 6'b100011://lw begin RegDst=0; ALUsrc=1; MemtoReg=1; RegWrite=1; MemRead=1; MemWrite=0; Branch=0; ALUOp[1]=0; ALUOp[0]=0; Jump=1; end

6'b101011://sw begin ALUsrc=1; RegWrite=0; MemRead=0; MemWrite=1; Branch=0; ALUOp[1]=0; ALUOp[0]=0; Jump=1; end

6'b000100://beq begin ALUsrc=0; RegWrite=0; MemRead=0;

MemWrite=0; Branch=1; ALUOp[1]=0; ALUOp[0]=1; Jump=1; end

6'b000010://j begin Jump=0; end endcase end

Endmodule

Dm.v

module dm_4k( addr, din, we, re,clk, dout ) ; input [11:2] addr ; // address bus input [31:0] din ; // 32-bit input data input we ; // memory write enable input re; //memory read enable input clk; // clock

output reg[31:0] dout ; // 32-bit memory output reg [31:0] dm[1023:0] ; initial begin

$monitor(\end

always @(posedge clk) begin if (we) begin

dm[addr[11:2]][31:0] = din[31:0]; end

if (re) begin

dout[31:0] = dm[addr[11:2]][31:0]; end end Endmodule

Extend.v

module SigExtend(origin,ext_result); parameter tem_WIDTH=16;

input[tem_WIDTH-1:0] origin; output[31:0] ext_result;

assign ext_result={{(32-tem_WIDTH){origin[tem_WIDTH-1]}},origin}; endmodule

Im.v

module im_4k( addr, dout ) ; input [11:2] addr ; // address bus output [31:0] dout ; // 32-bit memory output reg [31:0] im[1023:0] ; initial begin $readmemh(\ end assign dout = im[addr[11:2]][31:0]; Endmodule

Mips.v

`include \

`include \`include \`include \`include \`include \`include \`include \

`include \module mips(clk, rst); input clk ; // clock input rst ;// reset wire[31:0] cur_pc; wire[31:0] pcAlu_result; wire[31:0] next_pc; wire[31:0] pc_plus4; wire[31:0] branch_mux_result; wire[31:0] instruction; wire[4:0] wreg; wire[31:0] rdata1;

wire[31:0] rdata2; wire[31:0] extend; wire zero; wire[31:0] ALUresult; wire[31:0] rdata; wire[31:0] wdata; wire[31:0] aludata2; wire[3:0] alucontr; wire RegDst; wire Jump; wire Branch; wire MemRead; wire MemtoReg; wire[1:0]alu_op; wire MemWrite; wire ALUSrc; wire RegWrite; SigExtend ext(.origin(instruction[15:0]),.ext_result(extend)); assign pc_plus4=cur_pc+4; PC myPc(.clk(clk),.rst(rst),.address(next_pc),.out(cur_pc)); ALU pc_alu(.aluControl(4'b0010), .a(pc_plus4), .b({extend[29:0], 2'b00}), .result(pcAlu_result)); MUX32_2_1 #(32) brunch_mux(.A(pc_plus4), .B(pcAlu_result), .sel(Branch & zero), .result(branch_mux_result)); MUX32_2_1 #(32) jump_mux(.A({pc_plus4[31:28],instruction[25:0],2'b00}), .B(branch_mux_result),.sel(Jump), .result(next_pc)); im_4k myIM(.addr(cur_pc[11:2]),.dout(instruction)); controlUnit myCunit(.instruction(instruction[31:26]),.zero(zero),.RegDst(RegDst), .Jump(Jump),.Branch(Branch),.MemRead(MemRead),.MemtoReg(MemtoReg), .ALUOp(alu_op),.MemWrite(MemWrite),.ALUsrc(ALUsrc),.RegWrite(RegWrite)); RegFile myRF(.clk(clk),.we3(RegWrite),.ra1(instruction[25:21]),.ra2(instruction[20:16]), .wa3(wreg),.data(wdata),.rd1(rdata1),.rd2(rdata2)); MUX32_2_1

#(5)writeReg_mux(.A(instruction[20:16]),.B(instruction[15:11]),.sel(RegDst),.result(wreg)); dm_4k

myDM(.clk(clk),.addr(ALUresult),.din(rdata2),.we(MemWrite),.re(MemRead),.dout(rdata)); MUX32_2_1 #(32) regSrc(.A(ALUresult),.B(rdata),.sel(MemtoReg),.result(wdata)); ALUcontrol myALUcontr(.aluop(alu_op),.funct(instruction[5:0]),.aluControl(alucontr)); MUX32_2_1 #(32)alu_src(.A(rdata2),.B(extend),.sel(ALUsrc),.result(aludata2)); ALU myALU(.aluControl(alucontr),.a(rdata1),.b(aludata2),.result(ALUresult),.zero(zero));

endmodule;

Mux.v

module MUX32_2_1#(parameter Width = 32)(A,B,sel,result); input [Width-1:0] A,B; input sel; output [Width-1:0] result; assign result = (sel==1)?B:A; endmodule

Pc.v

module PC(clk,rst,address,out); input clk,rst; input [31:0] address; output reg[31:0] out;

always @(posedge clk) begin if(rst) out<=32'h00003000; else begin out<=address; end end endmodule

Rf.v

module RegFile(clk,we3,ra1,ra2,wa3,data,rd1,rd2); input clk,we3;

input[4:0] ra1,ra2,wa3; input[31:0] data; output[31:0] rd1,rd2;

reg[31:0] rf[31:0]; initial begin rf[0]=0; end

assign rd1=(ra1!=0) ? rf[ra1] : 0; assign rd2=(ra2!=0) ? rf[ra2] : 0;

initial begin

rf[0]=0; rf[1]=1; rf[2]=2; rf[3]=3; rf[4]=4; rf[5]=5;//a1 rf[6]=6;//a2 rf[7]=7;//a3 rf[8]=8;//t0 rf[9]=9;//t1 rf[10]=10;//t2 rf[11]=11;//t3 rf[12]=12;//t4 rf[13]=13;//t5 rf[14]=14;//t6 rf[15]=15;//t7 rf[16]=16;//$s0 rf[17]=17;//$s1 rf[18]=18;//$s2 rf[19]=19;//$s3 rf[20]=20; rf[21]=21;//s5 rf[22]=22;//s6 rf[23]=23; rf[24]=24; rf[25]=25;

rf[26]=26; rf[27]=27; rf[28]=28; rf[29]=29; rf[30]=30; rf[31]=31;

end

always @(posedge clk) begin if(we3)

rf[wa3]<=data; end

endmodule

Testbench.v

module testbench(); reg clk, rst; initial begin clk = 0; rst = 1; #12 rst = 0; end always #10 clk = ~clk; mips mips(.clk(clk), .rst(rst)); endmodule

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