NAND128W3A0BZA6F中文资料

元器件交易网

NAND128-A, NAND256-ANAND512-A, NAND01G-A

128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit (x8/x16)

528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories

FEATURES SUMMARY

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HIGH DENSITY NAND FLASH MEMORIES–––

Up to 1 Gbit memory arrayUp to 32 Mbit spare area

Cost effective solutions for mass storage applicationsx8 or x16 bus widthMultiplexed Address/ DataPinout compatibility for all densities1.8V device: VDD = 1.7 to 1.95V3.0V device: VDD = 2.7 to 3.6Vx8 device: (512 + 16 spare) Bytesx16 device: (256 + 8 spare) Wordsx8 device: (16K + 512 spare) Bytesx16 device: (8K + 256 spare) WordsRandom access: 12µs (max)Sequential access: 50ns (min)Page program time: 200µs (typ)

Fast page copy without external buffering

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NAND INTERFACE–––

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SUPPLY VOLTAGE––

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PAGE SIZE––

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BLOCK SIZE––

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PAGE READ / PROGRAM–––

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DATA INTEGRITY––

100,000 Program/Erase cycles10 years Data Retention

Lead-Free Components are Compliant with the RoHS Directive

Error Correction Code software and hardware models

Bad Blocks Management and Wear Leveling algorithms

File System OS Native reference softwareHardware simulation models

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COPY BACK PROGRAM MODE–

FAST BLOCK ERASE–

Block erase time: 2ms (Typ)

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RoHS COMPLIANCE–

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STATUS REGISTERELECTRONIC SIGNATURE

CHIP ENABLE ‘DON’T CARE’ OPTION–

Simple interface with microcontroller

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SERIAL NUMBER OPTIONHARDWARE DATA PROTECTION–

Program/Erase locked during Power transitions

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DEVELOPMENT TOOLS

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February 2005

元器件交易网

NAND128-A, NAND256-A, NAND512-A, NAND01G-A

Table 1. Product List

Reference

Part NumberNAND128R3A

NAND128-A

NAND128W3ANAND128R4ANAND128W4ANAND256R3A

NAND256-A

NAND256W3ANAND256R4ANAND256W4ANAND512R3A

NAND512-A

NAND512W3ANAND512R4ANAND512W4ANAND01GR3A

NAND01G-A

NAND01GW3ANAND01GR4ANAND01GW4A

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TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Figure 1.Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Table 1.Product List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Table 2.Figure 2.Table 3.Figure 3.Figure 4.Figure 5.Figure 6.Figure 7.Figure 8.Figure 9.

Product Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8Logic Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9TSOP48 and USOP48 Connections, x8 devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10TSOP48 and USOP48 Connections, x16 devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10FBGA55 Connections, x8 devices (Top view through package). . . . . . . . . . . . . . . . . . .11FBGA55 Connections, x16 devices (Top view through package). . . . . . . . . . . . . . . . . .12FBGA63 Connections, x8 devices (Top view through package). . . . . . . . . . . . . . . . . . .13FBGA63 Connections, x16 devices (Top view through package). . . . . . . . . . . . . . . . . .14

MEMORY ARRAY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Bad Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15Table 4.Valid Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15Figure 10.Memory Array Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15SIGNAL DESCRIPTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Inputs/Outputs (I/O0-I/O7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16Inputs/Outputs (I/O8-I/O15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16Address Latch Enable (AL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16Command Latch Enable (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161616 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161616VDD Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Command Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17Address Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17Data Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17Write Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17Table 5.Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17Table 6.Address Insertion, x8 Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

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Table 7.Address Insertion, x16 Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18Table 8.Address Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18COMMAND SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Table mands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19DEVICE OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Pointer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20Figure 11.Pointer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20Figure 12.Pointer Operations for Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21Read Memory Array. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22Random Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22Page Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22Sequential Row Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22Figure 13.Read (A,B,C) Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..23Figure 14.Read Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23Figure 15.Sequential Row Read Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24Figure 16.Sequential Row Read Block Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24Page Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Figure 17.Page Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25Copy Back Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26Table 10.Copy Back Program Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26Figure 18.Copy Back Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26Block Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27Figure 19.Block Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27Read Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28Write Protection Bit (SR7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28P/E/R Controller Bit (SR6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28Error Bit (SR0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28SR5, SR4, SR3, SR2 and SR1 are Reserved. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28Table 11.Status Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29Table 12.Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29SOFTWARE ALGORITHMS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Bad Block Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30Block Replacement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30Table 13.Block Failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30Figure 20.Bad Block Management Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30Figure 21.Garbage Collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31Garbage Collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31Wear-leveling Algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31Error Correction Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31Figure 22.Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31Hardware Simulation Models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

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Behavioral simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32IBIS simulations models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32PROGRAM AND ERASE TIMES AND ENDURANCE CYCLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Table 14.Program, Erase Times and Program Erase Endurance Cycles . . . . . . . . . . . . . . . . . . .33MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Table 15.Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Table 16.Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34Table 17.Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34Table 18.DC Characteristics, 1.8V Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35Table 19.DC Characteristics, 3V Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36Table 20.AC Characteristics for Command, Address, Data Input . . . . . . . . . . . . . . . . . . . . . . . . .37Table 21.AC Characteristics for Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38Figure mand Latch AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39Figure 24.Address Latch AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39Figure 25.Data Input Latch AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40Figure 26.Sequential Data Output after Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . .40Figure 27.Read Status Register AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41Figure 28.Read Electronic Signature AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41Figure 29.Page Read A/ Read B Operation AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42Figure 30.Read C Operation, One Page AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43Figure 31.Page Program AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44Figure 32.Block Erase AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45Figure 33.Reset AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45Ready/Busy Signal Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46Figure 34.Ready/Busy AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46Figure 35.Ready/Busy Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46Figure 36.Resistor Value Versus Waveform Timings For Ready/Busy Signal . . . . . . . . . . . . . . . .46PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Figure 37.TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline. . . . . . . . .47Table 22.TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data .47Figure OP48 – lead Plastic Ultra Thin Small Outline,12 x 17mm, Package Outline . . . . . . .48Table OP48 – lead Plastic Ultra Thin Small Outline, 12 x 17mm, Package Mechanical Data48Figure 39.VFBGA55 8 x 10mm - 6x8 active ball array, 0.80mm pitch, Package Outline . . . . . . . .49Table 24.VFBGA55 8 x 10mm - 6x8 ball array, 0.80mm pitch, Package Mechanical Data . . . . . .49Figure 40.TFBGA55 8 x 10mm - 6x8 active ball array - 0.80mm pitch, Package Outline. . . . . . . .50Table 25.TFBGA55 8 x 10mm - 6x8 active ball array - 0.80mm pitch, Package Mechanical Data50Figure 41.VFBGA63 9x11mm - 6x8 active ball array, 0.80mm pitch, Package Outline . . . . . . . . .51Table 26.VFBGA63 9x11mm - 6x8 active ball array, 0.80mm pitch, Package Mechanical Data. .51Figure 42.TFBGA63 9x11mm - 6x8 active ball array, 0.80mm pitch, Package Outline. . . . . . . . . .52Table 27.TFBGA63 9x11mm - 6x8 active ball array, 0.80mm pitch, Package Mechanical Data. .52

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PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Table 28.Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53APPENDIX A.HARDWARE INTERFACE EXAMPLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Figure43.Connection to Microcontroller, Without Glue Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . .54Figure 44.Connection to Microcontroller, With Glue Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55Figure 45.Building Storage Modules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..55RELATED DOCUMENTATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

Table 29.Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

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NAND128-A, NAND256-A, NAND512-A, NAND01G-A

SUMMARY DESCRIPTION

The NAND Flash 528 Byte/ 264 Word Page is afamily of non-volatile Flash memories that usesthe Single Level Cell (SLC) NAND cell technology.It is referred to as the Small Page family. The de-vices range from 128Mbits to 1Gbit and operatewith either a 1.8V or 3V voltage supply. The size ofa Page is either 528 Bytes (512 + 16 spare) or 264Words (256 + 8 spare) depending on whether thedevice has a x8 or x16 bus width.

The address lines are multiplexed with the Data In-put/Output signals on a multiplexed x8 or x16 In-put/Output bus. This interface reduces the pincount and makes it possible to migrate to otherdensities without changing the footprint.

Each block can be programmed and erased over100,000 cycles. To extend the lifetime of NANDFlash devices it is strongly recommended to imple-ment an Error Correction Code (ECC). A WriteProtect pin is available to give a hardware protec-tion against program and erase operations.

The devices feature an open-drain Ready/Busyoutput that can be used to identify if the Program/Erase/Read (P/E/R) Controller is currently active.The use of an open-drain output allows the Ready/Busy pins from several memories to be connectedto a single pull-up resistor.

A Copy Back command is available to optimize themanagement of defective blocks. When a PageProgram operation fails, the data can be pro-grammed in another page without having to re-send the data to be programmed.

The devices are available in the following packag-es:■TSOP48 12 x 20mm for all products■USOP48 12 x 17 x 0.65mm for 128Mb, 256Mb

and 512Mb products■VFBGA55 (8 x 10 x 1mm, 6 x 8 ball array,

0.8mm pitch) for 128Mb and 256Mb products■TFBGA55 (8 x 10 x 1.2mm, 6 x 8 ball array,

0.8mm pitch) for 512Mb Dual Die product■VFBGA63 (9 x 11 x 1mm, 6 x 8 ball array,

0.8mm pitch) for the 512Mb product■TFBGA63 (9 x 11 x 1.2mm, 6 x 8 ball array,

0.8mm pitch) for the 1Gb Dual Die productTwo options are available for the NAND Flashfamily:

Chip Enable Don’t Care, which allows code to bedirectly downloaded by a microcontroller, as ChipEnable transitions during the latency time do notstop the read operation.

A Serial Number, which allows each device to beuniquely identified. The Serial Number options issubject to an NDA (Non Disclosure Agreement)and so not described in the datasheet. For moredetails of this option contact your nearest ST Salesoffice.

For information on how to order these options referto Table 28.,Ordering Information Scheme. De-vices are shipped from the factory with Block 0 al-ways valid and the memory content bits, in validblocks, erased to ’1’.

See Table 2.,Product Description, for all the de-vices available in the family.

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Table 2. Product Description

Timings

Reference

Part Number

Density

Bus Width

Page Size

BlockSize

Memory Array

Operating Voltage1.7 to 1.95V

32 Pages x 1024 Blocks

2.7 to 3.6V1.7 to 1.95V2.7 to 3.6V1.7 to 1.95V

32 Pages x 2048 Blocks

2.7 to 3.6V1.7to 1.95V2.7 to 3.6V1.7to 1.95V

32 Pages x 4096 Blocks

2.7 to 3.6V1.7 to 1.95V2.7 to 3.6V1.7to 1.95V

32 Pages x 4096 Blocks

2.7 to 3.6V1.7 to 1.95V2.7 to 3.6V1.7 to 1.95V

32 Pages x 8192 Blocks

2.7 to 3.6V1.7 to 1.95V2.7 to 3.6V

Random Sequential Access AccessMaxMin12µs12µs12µs12µs12µs12µs12µs12µs12µs12µs12µs12µs15µs12µs15µs12µs15µs12µs15µs12µs

60ns50ns60ns50ns60ns50ns60ns50ns60ns50ns60ns50ns60ns50ns60ns50ns60ns50ns60ns50ns

Page

ProgramTypical200µs200µs200µs200µs200µs200µs200µs200µs200µs200µs200µs200µs200µs200µs200µs200µs200µs200µs200µs200µs

2ms

TSOP48TFBGA63

2ms

TSOP48USOP48VFBGA63

2ms

TFBGA55

2ms

TSOP48USOP48VFBGA55

2ms

TSOP48USOP48VFBGA55

Block EraseTypical

Package

NAND128R3A

NAND128-A

NAND128W3ANAND128R4ANAND128W4ANAND256R3A

NAND256-A

NAND256W3ANAND256R4ANAND256W4ANAND512R3A

NAND512-A(1)

NAND512W3ANAND512R4ANAND512W4ANAND512R3A

NAND512-A

NAND512W3ANAND512R4ANAND512W4ANAND01GR3A

NAND01G-A

NAND01GW3ANAND01GR4ANAND01GW4A

1Gbit512Mbit512Mbit256Mbit128Mbit

x8x16x8x16x8x16x8x16x8x16

512+16 16K+512 BytesBytes256+8 Words

8K+256 Words

512+16 16K+512 BytesBytes256+8 Words

8K+256 Words

512+16 16K+512 BytesBytes256+8 Words

8K+256 Words

512+16 16K+512 BytesBytes256+8 Words

8K+256 Words

512+16 16K+512 BytesBytes256+8 Words

8K+256 Words

Note:1.Dual Die device.

Table 3. Signal Names

I/O8-15

Data Input/Outputs for x16 devicesData Input/Outputs, Address Inputs, or Command Inputs for x8 and x16 devices

Address Latch EnableCommand Latch EnableChip EnableRead Enable

Ready/Busy (open-drain output)Write EnableWrite ProtectSupply VoltageGround

Not Connected InternallyDo Not Use

I/O0-7ALCLVDDVSSNCDU

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Figure 4. TSOP48 and USOP48 Connections,

Figure 5. TSOP48 and USOP48 Connections,

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MEMORY ARRAY ORGANIZATION

The memory array is made up of NAND structureswhere 16 cells are connected in series.

The memory array is organized in blocks whereeach block contains 32 pages. The array is splitinto two areas, the main area and the spare area.The main area of the array is used to store datawhereas the spare area is typically used to storeError correction Codes, software flags or BadBlock identification.

In x8 devices the pages are split into a main areawith two half pages of 256 Bytes each and a sparearea of 16 Bytes. In the x16 devices the pages aresplit into a 256 Word main area and an 8 Wordspare area. Refer to Figure 10.,Memory Array Or-ganization.Bad Blocks

The NAND Flash 528 Byte/ 264 Word Page devic-es may contain Bad Blocks, that is blocks that con-tain one or more invalid bits whose reliability is notguaranteed. Additional Bad Blocks may developduring the lifetime of the device. The Bad Block Information is written prior to ship-ping (refer to Bad Block Management section formore details).

Table 4. shows the minimum number of validblocks in each device. The values shown includeboth the Bad Blocks that are present when the de-vice is shipped and the Bad Blocks that could de-velop later on.

These blocks need to be managed using BadBlocks Management, Block Replacement or ErrorCorrection Codes (refer to SOFTWARE ALGO-RITHMS section).Table 4. Valid Blocks

Density of Device

1Gbit512Mbits256Mbits128Mbits

Min8032401620081004

Max8192409620481024

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SIGNAL DESCRIPTIONS

See Figure 2.,Logic Diagram, and Table3.,Signal Names, for a brief overview of the sig-nals connected to this device.

Inputs/Outputs (I/O0-I/O7).Input/Outputs 0 to 7are used to input the selected address, output thedata during a Read operation or input a commandor data during a Write operation. The inputs arelatched on the rising edge of Write Enable. I/O0-I/O7 are left floating when the device is deselectedor the outputs are disabled.

Inputs/Outputs (I/O8-I/O15).Input/Outputs 8 to15 are only available in x16 devices. They areused to output the data during a Read operation orinput data during a Write operation. Command andAddress Inputs only require I/O0 to I/O7.

The inputs are latched on the rising edge of WriteEnable. I/O8-I/O15 are left floating when the de-vice is deselected or the outputs are disabled.Address Latch Enable (AL).The Address LatchEnable activates the latching of the Address inputsin the Command Interface. When AL is high, theinputs are latched on the rising edge of Write En-able.

Command Latch Enable (CL).The CommandLatch Enable activates the latching of the Com-mand inputs in the Command Interface. When CLis high, the inputs are latched on the rising edge ofWrite Enable.

The Chip Enable input acti-vates the memory control logic, input buffers, de-coders and sense amplifiers. When Chip Enable islow, VIL, the device is selected.

While the device is busy programming or erasing,Chip Enable transitions to High, VIH, are ignoredand the device does not revert to the Standbymode.

While the device is busy reading:■the Chip Enable input should be held Low

during the whole busy time (tBLBH1) for

devices that do not present the Chip Enable Don’t Care option. Otherwise, the read

operation in progress is interrupted and the device reverts to the Standby mode. ■for devices that feature the Chip Enable Don't

Care option, Chip Enable going High during the busy time (tBLBH1) will not interrupt the read operation and the device will not revert to the Standby mode.the sequential data output during Read opera-tions. Data is valid t column address counter by one.

controls writing to the Command Interface, InputAddress and Data latches. Both addresses anddata are latched on the rising edge of Write En-able.

During power-up and power-down a recovery timeof 1µs (min) is required before the Command Inter-face is ready to accept a command. It is recom-mended to keep Write Enable high during therecovery time.

The Write Protect pin is aninput that gives a hardware protection against un-wanted program or erase operations. When WriteProtect is Low, VIL, the device does not accept anyprogram or erase operations.

It is recommended to keep the Write Protect pinLow, VIL, during power-up and power-down.is an open-drain output that can be used to identifyif the P/E/R Controller is currently active.

When Ready/Busy is Low, VOL, a read, program orerase operation is in progress. When the operationcompletes Ready/Busy goes High, VOH.

The use of an open-drain output allows the Ready/Busy pins from several memories to be connectedto a single pull-up resistor. A Low will then indicatethat one, or more, of the memories is busy.

Refer to the Ready/Busy Signal Electrical Charac-teristics section for details on how to calculate thevalue of the pull-up resistor.

VDD Supply Voltage.VDD provides the powersupply to the internal core of the memory device.It is the main power supply for all operations (read,program and erase).

An internal voltage detector disables all functionswhenever VDD is below 2.5V (for 3V devices) or1.5V (for 1.8V devices) to protect the device fromany involuntary program/erase during power-tran-sitions.

Each device in a system should have VDD decou-pled with a 0.1µF capacitor. The PCB track widthsshould be sufficient to carry the required programand erase currents

VSS Ground.Ground, VSS, is the reference forthe power supply. It must be connected to the sys-tem ground.

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BUS OPERATIONS

There are six standard bus operations that controlthe memory. Each of these is described in thissection, see Table 5.,Bus Operations, for a sum-mary.

Command Input

Command Input bus operations are used to givecommands to the memory. Command are accept-ed when Chip Enable is Low, Command Latch En-able is High, Address Latch Enable is Low andRead Enable is High. They are latched on the ris-ing edge of the Write Enable signal.

Only I/O0 to I/O7 are used to input commands. See Figure 23. and Table 20. for details of the tim-ings requirements.Address Input

Address Input bus operations are used to input thememory address. Three bus cycles are required toinput the addresses for the 128Mb and 256Mb de-vices and four bus cycles are required to input theaddresses for the 512Mb and 1Gb devices (referto Tables 6 and 7, Address Insertion).

The addresses are accepted when Chip Enable isLow, Address Latch Enable is High, CommandLatch Enable is Low and Read Enable is High.They are latched on the rising edge of the WriteEnable signal. Only I/O0 to I/O7 are used to inputaddresses.

See Figure 24. and Table 20. for details of the tim-ings requirements.Data Input

Data Input bus operations are used to input thedata to be programmed. Table 5. Bus Operations

Bus OperationCommand InputAddress InputData InputData OutputWrite ProtectStandby

VILVILVILVILXVIH

ALVILVIHVILVILXX

CLVIHVILVILVILXX

VIHVIHVIHFallingXX

RisingRisingRisingVIHXX

X(2)XXXVILX

I/O0 - I/O7CommandAddressData InputData Output

XX

I/O8 - I/O15(1)

XXData InputData Output

XX

Data is accepted only when Chip Enable is Low,Address Latch Enable is Low, Command LatchEnable is Low and Read Enable is High. The datais latched on the rising edge of the Write Enablesignal. The data is input sequentially using theWrite Enable signal.

See Figure 25. and Table 20. and Table 21. for de-tails of the timings requirements.Data Output

Data Output bus operations are used to read: thedata in the memory array, the Status Register, theElectronic Signature and the Serial Number.

Data is output when Chip Enable is Low, Write En-able is High, Address Latch Enable is Low, andCommand Latch Enable is Low.

The data is output sequentially using the Read En-able signal.

See Figure 26. and Table 21. for details of the tim-ings requirements.Write Protect

Write Protect bus operations are used to protectthe memory against program or erase operations.When the Write Protect signal is Low the devicewill not accept program or erase operations and sothe contents of the memory array cannot be al-tered. The Write Protect signal is not latched byWrite Enable to ensure protection even duringpower-up.Standby

When Chip Enable is High the memory entersStandby mode, the device is deselected, outputsare disabled and power consumption is reduced.

Note:1.Only for x16 devices.

IH when issuing a program or erase command.

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Table 6. Address Insertion, x8 Devices

Bus Cycle

1st2nd3rd4th(4)

I/O7A7A16A24VIL

I/O6A6A15A23VIL

I/O5A5A14A22VIL

I/O4A4A13A21VIL

I/O3A3A12A20VIL

I/O2A2A11A19VIL

I/O1A1A10A18A26

I/O0A0A9A17A25

Note:1.A8 is set Low or High by the 00h or 01h Command, see Pointer Operations section.

2.Any additional address input cycles will be ignored.

3.The 4th cycle is only required for 512Mb and 1Gb devices.

Table 7. Address Insertion, x16 Devices

Bus Cycle1st2nd3rd4th(4)

Note:1.

2.3.4.

I/O8-I/O15XXXX

I/O7A7A16A24VIL

I/O6A6A15A23VIL

I/O5A5A14A22VIL

I/O4A4A13A21VIL

I/O3A3A12A20VIL

I/O2A2A11A19VIL

I/O1A1A10A18A26

I/O0A0A9A17A25

A8 is Don’t Care in x16 devices.

Any additional address input cycles will be ignored.The 01h Command is not used in x16 devices.

The 4th cycle is only required for 512Mb and 1Gb devices.

Table 8. Address Definitions

AddressA0 - A7A9 - A26A9 - A13A14 - A26

A8

DefinitionColumn AddressPage AddressAddress in BlockBlock Address

A8 is set Low or High by the 00h or 01h Command, and is

Don’t Care in x16 devices

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COMMAND SET

All bus write operations to the device are interpret-ed by the Command Interface. The Commandsare input on I/O0-I/O7 and are latched on the risingedge of Write Enable when the Command LatchEnable signal is high. Device operations are se-lected by writing specific commands to the Com-Table 9. Commands

Command

Read ARead BRead C

Read Electronic SignatureRead Status RegisterPage ProgramCopy Back ProgramBlock EraseReset

Bus Write Operations(1)

1st CYCLE

00h01h(2)50h90h70h80h00h60hFFh

2nd CYCLE

-----10h8AhD0h-3rd CYCLE

------10h--YesYes

Command accepted

during busy

mand Register. The two-step commandsequences for program and erase operations areimposed to maximize data security.

The Commands are summarized in Table9.,Commands.

Note:1.The bus cycles are only shown for issuing the codes. The cycles required to input the addresses or input/output data are not shown.

2.Any undefined command sequence will be ignored by the device.

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