多功能ALU的设计和实现

多功能ALU的设计和实现——附VHDL源码（中） 2010年01月20日 星期三 12:13 转载请注明出处：

http://hi.http://www.wodefanwen.com//ouwennuan/blog/item/79943c32afdcbc48ad4b5fed.html alu74181.vhd(74181ALU芯片) library ieee;

use ieee.std_logic_1164.all; entity alu74181 is

port( );

--m为控制端,cn为最低位的进位输入 m,cn : in std_logic;

--s0~s3为控制参数,a0~a3、b0~b3为输入信号 s,a,b : in std_logic_vector(3 downto 0);

--g为进位发生输出,p为进位传送输出,co为本片的最后进位输出 g,p,co : out std_logic; --f0~f3为输出信号

f : out std_logic_vector(3 downto 0)

end alu74181;

architecture s_alu74181 of alu74181 is

--+++++++++++++++++++++++++++++++++++++++ --fmp函数发生器定义 component fpm is

port(s,a,b : in std_logic_vector(3 downto 0);

x,y : out std_logic_vector(3 downto 0));

end component;

--+++++++++++++++++++++++++++++++++++++++ --中间信号变量

--x0~x3,y0~y3为函数发生器输出信号 signal x,y: std_logic_vector(3 downto 0);

--sg,sp分别为临时存放进位发生输出和进位传送输出结果

--notm为对控制信号m取反 signal sg,sp,notm: std_logic; begin

--调用函数发生器

cmd : fpm port map(s,a,b,x,y); --求得输出信号f0~f3 notm <= not m;

f(0) <= x(0) xor y(0) xor ( not(notm and cn) ); f(1) <= x(1) xor y(1) xor

( not(

(notm and y(0))

or (notm and x(0) and cn)

) );

f(2) <= x(2) xor y(2) xor

( not(

(notm and y(1))

or (notm and x(1) and y(0)) or (notm and x(0) and x(1) and cn)

) );

f(3) <= x(3) xor y(3) xor

( not(

(notm and y(2))

or (notm and x(2) and y(1))

or (notm and x(0) and x(1) and x(2) and cn) or (notm and x(1) and x(2) and y(0))

) );

--求得进位发生输出g和进位传送输出p

sg <= y(3) or (y(2) and x(3)) or (y(1) and x(2) and x(3))

or (y(0) and x(1) and x(2) and x(3));

g <= sg;

sp <= x(0) and x(1) and x(2) and x(3); p <= sp;

--求得本片的最后进位输出co co <= not (

);

(sg and sp) or (sg and (not cn))

end s_alu74181;

cla74182.vhd(74182CLA芯片) library ieee;

use ieee.std_logic_1164.all; entity cla74182 is

port( );

--cn为最低位的进位输入 cn : in std_logic;

--ALU74181产生的进位发生输出g0~g3和进位传送输出p0~p3 g,p : in std_logic_vector(3 downto 0); --cx,cy,cz存放输出的组与组间的进位输出

--gg,pp存放输出的成组进位输出和成组进位传送输出 cx,cy,cz,gg,pp : out std_logic

end cla74182;

architecture s_cla74182 of cla74182 is

--存放cx,cy的中间信号变量 signal cxt,cyt : std_logic; begin

cxt <= g(0) or (p(0) and cn); cx <= cxt;

cyt <= g(1) or (p(1) and cxt); cy <= cyt;

cz <= g(2) or (p(2) and cyt);

gg <= g(3) or (g(2) and p(3)) or (g(1) and p(2) and p(3))

or (g(0) and p(1) and p(2) and p(3));

pp <= p(0) and p(1) and p(2) and p(3);

end s_cla74182;

alu16.vhd(16位的全先行进位的ALU) library ieee;

use ieee.std_logic_1164.all; entity alu16 is

port( );

--m为控制端,cn为最低位的进位输入 m,cn : in std_logic; --s0~s3为控制参数

s : in std_logic_vector(3 downto 0); --a0~a15、b0~b15为输入信号

a,b : in std_logic_vector(15 downto 0); --co为最后进位输出 co : out std_logic; --f0~f15为输出信号

f : out std_logic_vector(15 downto 0)

end alu16;

--alu74181元件函数定义

component alu74181 is

port( );

m,cn : in std_logic;

s,a,b : in std_logic_vector(3 downto 0); g,p,co : out std_logic;

f : out std_logic_vector(3 downto 0)

end component;

--+++++++++++++++++++++++++++++++++++++++ --cla74182元件函数定义 component cla74182 is

port( );

cn : in std_logic;

g,p : in std_logic_vector(3 downto 0); cx,cy,cz,gg,pp : out std_logic

end component; --fmp函数发生器定义 component fpm is

port(s,a,b : in std_logic_vector(3 downto 0);

x,y : out std_logic_vector(3 downto 0));

end component;

--+++++++++++++++++++++++++++++++++++++++ --中间信号变量 signal

--sa1~sa4存放输入信号a0~a15

sa1,sa2,sa3,sa4,

--sx1~sx4存放输入信号a0~a15经函数发生器处理后的结果

sx1,sx2,sx3,sx4,

--sb1~sb4存放输入信号b0~b15

sb1,sb2,sb3,sb4,

--sx1~sx4存放输入信号b0~b15经函数发生器处理后的结果

sy1,sy2,sy3,sy4,

--sf1~sf4存放输出信号f0~f15

sf1,sf2,sf3,sf4,

--存放由4片ALU74181产生的进位发生输出sg0~sg3和进位传送输出sp0~sp3

sg,sp,sg1,sp1 : std_logic_vector(3 downto 0);

signal

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