A 20 mV Input Boost Converter With Efficient Digital Control

IEEE JOURNAL OF SOLID-STATE CIRCUITS,VOL.45,NO.4,APRIL 2010741

A 20mV Input Boost Converter With Ef?cient Digital Control for Thermoelectric Energy Harvesting

Eric J.Carlson,Kai Strunz,and Brian P.Otis ,Member,IEEE

Abstract—This paper presents a low power boost converter for thermoelectric energy harvesting that demonstrates an ef?ciency that is 15%higher than the state-of-the-art for voltage conversion ratios above 20.This is achieved by utilizing a technique allowing synchronous recti?cation in the discontinuous conduction mode.A low-power method for input voltage monitoring is presented.The low input voltage requirements allow operation from a thermoelec-tric generator powered by body heat.The converter,fabricated in a

0.13m CMOS process,operates from input voltages ranging from 20mV to 250mV while supplying a regulated 1V output.The converter consumes 1.6

(1.1)W of quiescent power,delivers up to 25

(175)W of output power,and is 46(75)%ef?cient for a 20mV and 100mV input,respectively.

Index Terms—Boost converter,discontinuous conduction mode,energy harvesting,low power,low voltage,power scavenging,pulse-frequency modulation,synchronous DC-DC converter.

I.I NTRODUCTION

F

OR wireless systems such as implantable medical sen-sors and animal tracking devices,battery replacement may be dif?cult or impossible.Emerging battery-free power sources (small thermoelectric generators,inpidual solar cells,micro-bial fuel cells)provide signi?cantly less than the voltage re-quired (around 1V)for most state-of-the-art integrated circuits.For example,thermoelectric energy harvested from machines,aircraft,and even body heat can be used as a virtually indef-inite power supply for such circuits.However,there are many challenges associated with converting thermal energy from body heat to electrical energy [1],[2].A thermoelectric generator (TEG)generates a voltage that is proportional to the difference of the temperatures applied to each side.One side is placed ei-ther on the warm skin or under the skin,while the other side is exposed to the cooler ambient air.Although the body temper-ature of the subject is well regulated,the ambient temperature,air?ow,and thermal insulation due to clothing varies widely.Therefore,a DC-DC converter that can accommodate a widely-varying and low voltage source and boost it to a regulated supply is needed to operate low-power circuitry.Because our target load circuitry consumes

10W of average power or less,the

Manuscript received August 24,2009;revised January 15,2010.Current ver-sion published March 24,2010.This paper was approved by Guest Editor Ajith Amerasekera.

E.Carlson was with the Department of Electrical Engineering,University of Washington,Seattle,W A 98195USA.He is now with National Semiconductor Corporation,Federal Way,W A 98001USA (e-mail:Eric.Carlson@7ca2db25bcd126fff7050b31).K.Strunz is with the Technische Universit?t Berlin,10587Berlin,Germany (e-mail:kai.strunz@tu-berlin.de).

B.P.Otis is with the Department of Electrical Engineering,University of Washington,Seattle,W A 98195USA (e-mail:botis@7ca2db25bcd126fff7050b31).Digital Object Identi?er 10.1109/JSS

C.2010.2042251

converter must have very low quiescent power consumption in order to ef?ciently drive the low-power load.This paper presents a switched-mode boost converter that can step up voltages be-tween 20mV and 250mV to ef?ciently provide a controllable voltage of approximately 1V to a

10W load.Section II ex-plains the control method used to achieve synchronous recti?-cation in discontinuous conduction mode (DCM)that facilitates ef?cient low-voltage low-power operation.Section III provides an overall block diagram of the boost converter circuit with de-scriptions of each block.Section IV explains how design param-eters were optimized to maximize ef?ciency.Section V presents measured results and compares to the state-of-the-art.II.S YNCHRONOUS R ECTIFICATION T HROUGH P EAK

C URRENT -M ODULATION

A diagram of an ideal boost converter is shown in Fig.1(a).Boost converters typically operate in one of two modes:contin-uous conduction or discontinuous conduction [3].The main dif-ference is that,in the continuous conduction mode (CCM),the inductor current can ?ow negative if the load is small enough.In contrast,in the discontinuous conduction mode (DCM),the in-ductor current is prevented from ?owing negative.The DCM is more ef?cient when the average input current is less than half the ripple current because the CCM will discharge the output capac-itor during the part of the switching cycle when the inductor cur-rent ?ows negative,increasing switching losses [4].By utilizing pulse-frequency modulation (PFM),the ef?ciency can be fur-ther improved at low power levels because the switching losses scale with the output power.As illustrated in Fig.2,when oper-ating in the DCM,the high-side switch turns off before the cur-rent ?ows negative,thereby maximizing the net charge placed on the output capacitor per switching 7ca2db25bcd126fff7050b31ing a diode for the high-side switch,as shown in Fig.1(b),would be inef?cient due to the high forward voltage drop.A pFET can be used as the high-side switch to avoid this voltage drop,as in Fig.1(c).The challenge therefore is in synchronizing the high-side switch

with the moment that the current falls to

zero

.A.Synchronous Recti?cation Methodologies

For maximum ef?ciency,the pFET should turn off just as the inductor current falls to zero.A feedback mechanism is needed to drive the current zero-crossing as close as possible to the

pFET turn-off

instant

.One technique is to use a reactive gate control method that uses a comparator to detect when the pFET becomes reverse biased and subsequently trigger a pulse to disable the switch [5].This method is problematic because it requires a very fast (on the order of 1/4the pFET on-time of 40ns)comparator evaluation and gate driver for the pFET.Sig-ni?cant latency in the detection process will allow the inductor

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Fig.1.A boost converter using (a)ideal switches,(b)a diode as the high-side switch,and (c)a pFET as the high-side switch,to step up voltage from a TEG to drive a low-power

load.

Fig.2.Discontinuous conduction mode (left)is more ef?cient than continuous conduction mode (right)at low power levels because it does not allow the current through the pFET high side switch to ?ow negative.

current to ?ow negative,dramatically reducing the converter ef-?ciency.An offset can be introduced into the comparator to counteract the latency,as described in [6],but this method is subject to variations in the slope of the falling current

waveform

.An alternative is to use an adaptive circuit that senses when the pFET turns off,compares that to when the pFET becomes reverse biased,and adjusts the time duration that the pFET is on for the next cycle accordingly [7].Though this solution solves the latency problem,it still requires a comparator to sense the polarity of the current.Since the target quiescent power dissipa-tion is around

1W,static comparator bias current is undesir-able.

B.Proposed Method

Our proposed synchronization method,illustrated in Fig.3,requires no analog circuitry and is thus nearly free of static cur-rent dissipation.If the pFET is turned off early (before the in-ductor current falls to zero),the pFET will continue to conduct,but with a much higher voltage drop.The result is that

the node stays high,even after the pFET is switched off.The voltage will stay high until the inductor current ?nally falls to zero.

On

Fig.3.Left:If the power FET drain voltage (

v )is high after the pFET is switched off,then the current fell to zero after the pFET was switched off.Right:If the drain voltage is low after the pFET is switched off,then the current fell to zero before the pFET was switched off.

the other hand,if the pFET is turned off late,

the voltage will fall to zero very quickly after the pFET is ?nally switched off.

Since only the logic level

of

needs to be detected,a static CMOS ?ip-?op can be used for the operation.Therefore,by sampling the high/low state of the drain voltage shortly after the pFET is switched off,one can determine whether the pFET was turned off before or after the current falls to zero.

The logic threshold of the ?ip-?op is skewed high (more than 50%of the output voltage)in order to quickly detect

when transitions low and also to prevent a false reading from ringing

on

the

node.The duration of the delay is set as short as possible while ensuring that across process/voltage/temperature (PVT)the delay is always longer than the time it takes

the node to transition low (assuming zero inductor current at the time that the pFET is switched off).If the delay is too fast,

the ?ip-?op will always sample

the

node to be high.The width of

the overshoot

pulse is proportional to the delay time.It is desirable to minimize the width of this overshoot pulse because during that time the pFET is conducting with a much higher resistance.

To synchronize the pFET turn-off with the inductor current zero-crossing,we have chosen to adjust the peak

current in-stead of the pFET switch

timing .Increasing ,for example,

increases the time that it takes the current to fall to

zero

.This choice is appropriate since the nFET on-time is much longer than the pFET on-time,and thus easier to control.The peak current is adjusted by changing the duration that the nFET

switch is

on

.The current

rise-time is set by the frequency of the on-chip oscillator that drives the nFET gate.The frequency control circuit in Fig.4adjusts the oscillator

frequency to

make

equal

to .The ?ip-?op samples the binary state of

the voltage shortly after the rising edge of the pFET gate voltage.The sampled state informs the counter to either count up (decrease the oscillator period)or count down (increase the oscillator period).Thus,the counter acts as an integrator in the feedback loop.If the sampled state is high,

then the counter increments

and

,,

and all decrease for the next switching cycle.If

the

state is low,then the counter decrements,

causing

,,

and to increase for the next cycle.The result is that,in steady state,the current will

CARLSON et al.:A20mV INPUT BOOST CONVERTER WITH EFFICIENT DIGITAL CONTROL FOR THERMOELECTRIC ENERGY HARVESTING

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Fig.4.Boost converter block diagram.

toggle above and below the target current value(Fig.3).The voltage supervisor,which is not part of the gate synchronization circuit,sets the desired converter output voltage.

C.Input Voltage Estimation

Knowing the input voltage is important when operating a DC-DC converter powered from harvested energy because the available power at the input is often severely limited by the in-ternal resistance of the power source.A TEG,which has an ap-proximately constant internal resistance[8],will deliver max-imum output power when the load is impedance matched.If the boost converter pulls its input voltage below half the open circuit voltage and the converter continues to output constant power, then the TEG output power will continuously decrease and the voltage will drop,discharging the input?lter capacitor,until it becomes too low for the converter to function.By monitoring the input voltage,the controller can deny power to the load and thereby reduce the power drawn from the TEG when the input voltage becomes too low.

The transfer function of an ideal boost converter

is

(1)

If the control circuit knows the ratio

between

and,

and the output voltage is controlled to a known value,then the

input voltage can be estimated without the need for additional

voltage monitoring circuitry such as an ADC.Our timing syn-

chronization technique is suitable for input voltage estimation

because

and are both driven by the same digital clock,

and therefore the ratio can be easily determined as shown in the

next

section.

Fig.5.Theoretical circuit waveforms.

III.C IRCUIT B LOCK D ESCRIPTIONS

The circuit block diagram is shown in Fig.4.Fig.5pro-

vides the power FET switching

signals and drain cur-

rents,along with the drain node

voltage and

the output

voltage.The main circuit components are the

power FETs,voltage supervisor,voltage pider,oscillator,fre-

quency control,

one-shot,?lter,and zero compare blocks.

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Fig.6.Digitally controlled oscillator and one-shot block diagram.

Also,the circuit requires three off-chip passive components:and inductor and two ?lter capacitors.A.Power FETs

The power FETs are dual-gate MOSFETs that can withstand drain-source voltages up to 2.6V.The high voltage tolerance comes at the expense of higher channel resistance,but is needed

because the drain voltage can

exceed

plus (which could

total 1.5V.To avoid latch-up,the pFET and nFET were laid out with

30m spacing and surrounded by

10m guard rings.B.Voltage Supervisor and Voltage Divider

The voltage supervisor and the bias circuitry are the only blocks that consume static power.This supervisor monitors the output voltage and activates an on-chip clock when the output

voltage is below

2

.All circuits are idle until the voltage supervisor output transitions high.The voltage supervisor delay speci?cations are not stringent,though it is preferable to be faster than half the oscillator period (320ns minimum period)to minimize output voltage ripple.A switched-capac-itor voltage pider is used to scale down the output voltage before entering the voltage supervisor.The switched capacitor topology eliminates the static bias current inevitable with a resistive pider.Equal value switched capacitors provide an accurate 2X voltage pision.Each capacitor is 0.9pF,which is large enough such than the input capacitance of the voltage supervisor and other parasitic capacitances do not signi?cantly affect the pided voltage (less than 5%error). C.Oscillator and One-Shot

The oscillator and one-shot circuits set the on-time of the

switching

nFET

and

pFET ,

respectively.is equal to the duration that the oscillator is high for each

cycle.is equal to the clock period (40ns)and is approximately equal

to

due to the synchronization feedback.From (1),it can be seen that in order to support an input voltage of 20mV with

an output voltage of 1V

,

will be approximately 50times greater

than

(in reality it will be about 60due to voltage drop from parasitic resistances).For a 200mV

input,

will be 4.5times greater

than

.Therefore,the oscillator must have a controllable output pulse-width ranging between 4and

60times greater

than

.The oscillator circuit and the one-shot circuit are shown in detail in Fig.6.A gated ring oscillator generates the 50MHz clock that drives the control logic.The clock is enabled when the signal from the comparator transitions high.A latch prevents circuit interruption partway through a switching cycle.An ex-ternal bias (supplied

by

in Fig.4)allows external manipu-lation of the frequency for experimentation.Though we expect the frequency to have a signi?cant temperature coef?cient,the boost converter maintains functionality for frequency variations up to 25%.Because the oscillator and the one-shot circuits are driven by the same clock,this topology ensures that the time

that the nFET is

on

is always a well de?ned multiple of the time that the pFET is

on,

.The oscillator circuit contains two sub-blocks.The shift reg-ister ring oscillator block creates a 50%duty cycle square-wave with a period adjustable by 40ns steps.This signal then enters an N-stage frequency pider to allow a wide frequency control range.The result is a 50%duty cycle square wave that can have

CARLSON et al.:A 20mV INPUT BOOST CONVERTER WITH EFFICIENT DIGITAL CONTROL FOR THERMOELECTRIC ENERGY HARVESTING

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Fig.7.Relationship between the oscillator output period and the digital input control word.

a period ranging from 320ns up to 4480ns (frequency range of 220kHz to 3.1MHz)with approximately 20%increments.This

allows

to be adjustable between 160ns and 2240ns while only requiring 4control bits.The relationship between the input control word and the output period is shown in Fig.7.

Reducing the quantization error of the controllable period by adding more control bits comes at the expense of circuit com-plexity and integrator (counter)response time.

Since

is only adjusted by one increment per switching cycle,a smaller step size would result in slower response times to sudden

changes in input voltage.A 20%

worst-case

inaccuracy results from our 4-bit control,creating an approximately 5%reduction in ef?ciency.A 4-bit control word means that the worst-case time that it would take the oscillator frequency to increment to the steady-state value would be 15switching cycles

(20s for a

10W load).

The one-shot output feeds into the pFET gate driver.The one-shot circuit transitions low immediately after the nFET turns off (when the oscillator goes low)and stays low for one clock cycle (40ns)before transitioning back high.Therefore,the du-ration that the pFET is

on

is equal to the clock period.The peak inductor

current is directly proportional

to

and when the synchronization feedback is working properly.There-fore,the peak inductor current can be controlled by adjusting the clock frequency.D.Zero Compare

To prevent the boost converter from pulling the TEG voltage below 20mV ,a switch

(M in Fig.4)is used in the load cur-rent return path.When the digital control signal to the oscillator block reaches zero,the input voltage is considered critically low and the zero-compare circuit switches off the load in order to allow the input voltage to recover.Because the input voltage is so low,the internal control circuitry must be powered from the output of the converter.This means that the output capacitor must be charged to at least 600mV before the boost converter can operate.If the stored output voltage drops below approxi-mately 600mV ,the power FETs will fail to turn on suf?ciently,creating a prohibitively large on-resistance and causing the cir-cuit to fail.E.Startup

A signi?cant problem with this type of voltage converter is startup.For the conditions described in this paper,a

one-time

Fig.8.Boost converter diagram showing the parasitic resistances of the power FETs and the inductor,along with the parasitic capacitance at the

V node.

precharge of the load capacitor was used to startup the converter.If an energy storage element such as battery or supercapacitor is present in the system,it can store charge while the converter is disabled for long periods of time.When the voltage from the TEG returns to usable levels,the charge from the storage element would revive the converter.If the storage element is completely discharged,a low-power switched capacitor circuit could be used to generate the 600mV needed for startup.Since a limited amount of energy is required for startup,the switched capacitor circuit needs neither high ef?ciency nor high output power.

F .Bias Generator and References

The bias generator distributes the necessary currents for the clock circuit and the voltage supervisor.This block consumes 200

nA from an externally generated current reference.An external voltage reference sets the regulated output voltage.A bandgap reference and regulator combination similar to the one in [9]can be used to generate on-chip references,which will consume approximately 250nA of additional current,thereby reducing the overall ef?ciency by roughly 2%for a

10W load.

IV .D ESIGN M ETHODOLOGY

Maximizing conversion ef?ciency is important when the input power comes from an energy harvesting device such as a TEG due to the inherent output power limitations of the TEG.In order to maximize the ef?ciency of the converter,one must understand the tradeoffs associated with each design choice.Design parameters such as the power FET sizes,peak inductor current,and inductor choice all need to be optimized to provide the best ef?ciency.However,functionality requirements such as limits on maximum output power,voltage ripple,and total die/PCB area must also be considered.Our design target was on for an input voltage of 50mV ,an output voltage of 1V ,and an output power of

10W.A.Ef?ciency Calculation

A model was built to understand how each design parameter affects ef?ciency.Fig.8shows a representation of the boost converter including the primary sources of power losses.The inductor and power FETs each have parasitic resistances that result in conduction losses,and the parasitic capacitance at

the

node along with the power FET gate capacitances cause switching losses.If we assume that the input voltage ripple and output voltage ripple are small,and the voltage drop from the parasitic resistances of the inductor and nFET are much smaller

746IEEE JOURNAL OF SOLID-STATE CIRCUITS,VOL.45,NO.4,APRIL2010 than the input voltage,a reasonably accurate ef?ciency model

can be derived[10].

The ef?ciency of the boost converter

is

(2)

where is the energy delivered to the load

and is the

energy drawn from the source during one switching cycle.

Equation(2)can be expanded to show each source of

losses:

-

-

(3)

-

and

-are the energy required to drive the gates

of the power nFET and

pFET,is the energy lost due to

driving the parasitic capacitance on

the node,

and is the

energy consumed by the control

logic.

,,

and

are the conduction losses due to the parasitic resistances of the

nFET,pFET,and inductor,respectively.The?nal term takes

into account the static power losses due to the voltage super-

visor

circuit.

,the amount of energy that is converted to the higher

voltage per cycle,

is

(4)

where the?rst term is the energy stored in the inductor

during

,the second is the energy that enters the converter

during

,the third is the energy required to charge

the capaci-

tance,and the?nal term is the energy lost due to the inductor

and pFET parasitic resistances.

The rising time and falling time of the inductor current

are

(5)

and

(6)

represents energy losses due to synchronization error

of the power FET gate timing.If the pFET is turned off before

the current reaches zero,the synchronization losses come from

increased voltage drop of the pFET during the overshoot time

(,Fig.

3):

(7)

where in this case is the ideal pFET on-time to achieve

exact synchronization.If the pFET is turned off after the current

has crossed zero,then the synchronization losses come from the

output being discharged during the negative conduction

time:

(8)

TABLE I

E STIMATED B REAKDOWN O

F L OSSES(P ERCENTAGE OF T OTAL L OSSES)

F ROM S IMULATED D ATA(V=1V;P=10 W

)

It can therefore be determined that overall ef?ciency is not sen-

sitive to synchronization

error,.If the error is20%

of,

then only4%of the total output energy is lost.

Table I shows a breakdown of the boost converter losses

estimated from simulation data for input voltages25mV

and200mV.Losses due to resistance of the nFET and the

inductor are more dominant in the25mV case because the

nFET and inductor are conducting for a longer period of time

for each switching cycle

(is greater

for25mV)

and therefore more energy is consumed per cycle.The pFET is

on for the same amount of time for both cases

(constant)

and therefore the energy lost due to the pFET resistance is

also constant.The control circuitry consumes signi?cantly less

power when the input voltage is200mV

because is shorter

and therefore it takes fewer clock cycles for the converter to

complete one switching cycle.

B.Voltage Ripple

Besides ef?ciency,input and output voltage ripple must also

be considered.The input voltage ripple

is

(9)

In

general,should be the largest capacitor possible in

order to minimize input voltage ripple.A ripple voltage of5%is

considered suf?cient for most applications(1mV of ripple for

a20mV input).A2.0

mm 1.2mm

10F input capacitor was

used to achieve this requirement.

Likewise,the output voltage ripple

is

(10)

The requirements for the output voltage ripple are deter-

mined by what the load can tolerate.For our low power wireless

sensing applications,20mV of ripple is considered suf?ciently

small,and is achieved with a1.0

mm0.5mm10nF output

capacitor.

C.Inductor

The inductor choice is critical for ef?cient boost converter op-

eration.According to(4),a larger inductor value provides more

CARLSON et al.:A20mV INPUT BOOST CONVERTER WITH EFFICIENT DIGITAL CONTROL FOR THERMOELECTRIC ENERGY HARVESTING747

energy transfer per switching

cycle.This improves ef?-

ciency because,as seen in(3),the constant gate drive losses be-come less signi?cant compared to a larger output energy.Dou-bling the inductance effectively reduces the gate drive power losses by one-half because the converter only needs to switch half as often.

On the other hand,increasing the inductance generally comes at the expense of either physical size or parasitic series resis-tance.Doubling the inductance will nearly double the parasitic series resistance if the case size is kept constant[11].The losses due to inductor series resistance

are

(11)

We determined that a

4.7H inductor

with230

m

and a2.0

mm 2.0mm footprint provides an appropriate

tradeoff between resistive losses,switching losses,ripple,and

area.

D.Power FETs

The losses of the power nFET and pFET are a tradeoff be-

tween conduction losses due to parasitic channel resistance and

gate-drive losses due to parasitic gate capacitance.The gate-

drive losses are proportional to the effective transistor width,

while the channel resistance is inversely proportional to the tran-

sistor width.The conduction losses for the pFET and nFET are

as

follows:

(12)

(13)

Because the gate drivers are powered from the boost con-

verter’s output,the effective losses are ampli?ed by the ef?-

ciency of the

converter:

-

-(14)

An optimum ef?ciency tradeoff is achieved when the widths

of the nFET and pFET are such

that

(15)

where is the width of either power FET device.The widths

for the nFET and pFET were chosen to be4.5mm and1.5mm,

respectively.

E.Peak Current Control

Section II stated that the peak inductor

current was chosen

to be the adjustable parameter to

control such that it is equal

to,rather than directly

adjusting to match

with.

According to(6),

for,the peak inductor

current

is directly proportional

to

:

(16)

Fig.9.Boost converter circuit micrograph.

While

and are held

constant,also remains rela-

tively constant as long

as.It can be inferred from

the prior ef?ciency analysis that

keeping constant for

varying

enables higher ef?ciency for low input voltages and reduces

output voltage ripple for higher output voltages[12].From(4)

it is apparent

that is very sensitive to.If we were to use

a control topology that keeps the nFET gate

timing con-

stant and adjusts the pFET gate

timing to achieve

equal

and,

then would be approximately proportional

to the square of the input voltage.The result would be almost

zero transferred energy at very low input voltages and exces-

sive output voltage ripple with higher input voltages.The peak

current also limits the maximum average input current,which

therefore limits the maximum output

power:

(17)

where is the duty cycle of output of the oscillator block.

V.M EASURED R ESULTS

The circuit was fabricated in a

0.13m CMOS process.Fig.9

shows the die micrograph.The active area is:

35,000m for

the power FETs and gate drivers,

12,000m for the control cir-

cuitry,and

70,000m for output voltage?lter capacitors.Para-

sitic resistance on the input and ground pins must be minimized.

For example,100

m added in series with the inductor can de-

grade ef?ciency by3%.To minimize this resistance,we use

three pads for ground and two pads for

the node.The chip

was assembled onto a PCB using chip-on-board wirebonding.

A.Waveforms

The output capacitor was initially precharged to1V and an

input voltage of50mV was provided,and the converter was

loaded with a100

k resistor

(10W load).Fig.10shows the

ripple of the output

voltage and the power FET drain

voltage.The reference

voltage was adjusted such that

the average output voltage was exactly1V.The ripple voltage

alternates between10mV and15mV due to the quantization of

the frequency control circuit,which is continuously stepping up

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Fig.10.Top:Power FET drain voltage (

v ).Bottom:Converter output voltage

ripple (average voltage is 1

V).

Fig.11.Measured drain voltage waveform with persistence enabled.V =

50mV,V =1V,P =10 W.

and down to

keep on average equal

to ,as illustrated in Figs.3and 5.

Fig.11shows a close up view of

the

voltage.The pFET

on-time

can be inferred from the waveform to be about 40ns.Persistence was enabled on the oscilloscope to show

that

cycles between two discrete values.For one

cycle,is high for about 5ns longer than the other,and it can be seen that the drain voltage increases by about 200mV toward the end of the conduction time because the current is still ?owing after pFET is switched off.B.Performance

The ef?ciency of the converter was measured for a variety of input voltages and loads.The results given in Fig.12show that the ef?ciency is somewhat ?at for input voltages above 75mV.In this range the ef?ciency is dominated by switching losses,which are mostly independent of input voltage.When the input voltage is below 75mV ,the ef?ciency becomes dom-inated by conduction losses,which become more prominent as the input voltage becomes closer to the voltage drops of the para-sitic resistances.When the load power approaches the quiescent converter power,(roughly

1W),the ef?ciency degrades sig-ni?cantly.The lowest input voltage where the boost converter can drive a

1W load is 16mV ,with 13%ef?ciency.There is a sudden ef?ciency improvement when the input voltage

is

Fig.12.Measured converter ef?ciency versus input voltage for different loads.V =1

V.

Fig.13.Measured ef?ciency versus output voltage for V =50mV,P =

10 W.

240mV because at this voltage the counter in the frequency

control circuit has saturated high

and does not change be-tween cycles.

Fig.13shows the ef?ciency versus the output voltage for a 50mV input and a

10W load.The converter is most ef?cient when the output voltage is 0.9V ,while the ef?ciency quickly degrades as the output voltage drops below 0.7V.The ef?ciency reduction at low output voltages is primarily due to the increased switch resistances resulting from less voltage applied to the FET gates,while the ef?ciency reduction at higher voltages is due to the increase in energy required to drive the FET gates and the control logic.

Table II provides a summary of the boost converter perfor-mance.Unloaded,the boost converter can operate in input volt-ages down to 15mV before the losses become too great to sus-tain a voltage at the output.Although the converter will function with input voltages above 250mV ,the frequency control circuit saturates beyond this point and the gate-timing synchronization feedback mechanism ceases to function properly.The converter supports output voltages up to 1.4V:voltages beyond this ex-ceed the voltage ratings of the transistors.If the output voltage drops below 600mV ,the power FETs can no longer be suf?-ciently switched on,and the converter will not 7ca2db25bcd126fff7050b31parison With Prior Work

To the best of the authors’knowledge,this paper reports the highest ef?ciency 20mV input boost converter to date.Ref.[13]reports 20mV to 3.4V conversion,but an “average”ef?ciency of 30%.Other low power and low voltage step-up converters

CARLSON et al.:A 20mV INPUT BOOST CONVERTER WITH EFFICIENT DIGITAL CONTROL FOR THERMOELECTRIC ENERGY HARVESTING 749

TABLE II

B OOST

C ONVERTER P ERFORMANCE S

UMMARY

Fig.14.Ef?ciency comparison between this work (V

=1V )and [16]

(V

=4.2V ).typically operate either with much higher quiescent power con-sumption [14],or have low step-up ratios [15].Ref.[16]is the only work that we have seen that achieves ef?cient operation for a conversion ratio greater than 10and load power on the order of

10W with suf?cient data for comparison.Fig.14compares the ef?ciency results with those achieved in [16].Because [16]operates with higher output voltages (4.15V),results are com-pared normalized to voltage conversion ratios.It can be seen that for conversion ratios above 8,this work achieves signif-icantly greater ef?ciency,which can be attributed to low qui-escent power consumption and optimum device size selection.The circuit in [16]does not suffer from severe losses from the high-side diode voltage drop because the output voltage is much higher than the voltage drop.

D.Characterization With a Thermoelectric Generator We have performed some initial characterization of the boost circuit connected to a 1cm thermoelectric generator.The TEG has an internal resistance of

3.9.Fig.15shows the maximum power that could be extracted from the TEG given an applied temperature.The temperature is given relative to ambient tem-perature (24C).A 4C temperature differential is required to get

the 20mV input voltage required for ef?cient operation.The circuit was then tested with body heat from a human arm.The converter was allowed to reach thermal equilibrium over a period of 10minutes.At equilibrium,the generator produced 34mV (unloaded voltage)and the boost converter was able to deliver

34W at 1

V.

Fig.15.The unloaded (open circuit)voltage generated by the TEG and the maximum power deliverable at 1V versus the temperature difference of the hot side of the TEG from ambient (ambient temperature is 24C).

VI.C ONCLUSION

Many emerging energy-harvesting power sources such as TEGs fail to provide the voltages needed for low power wireless sensors.We have demonstrated that a switched-mode DC-DC boost converter can ef?ciently generate a 1V output from input voltages as low at 20mV.A novel control circuit uses peak current regulation to allow ef?cient operation for input voltages ranging between 20mV and 250mV ,while consuming less than

2W of quiescent power.The control circuit includes a load control feature that disables the load when input voltages become critically low.It was also shown that the conversion ef?ciency from this work is signi?cantly greater than that found in prior work for high conversion ratio low power boost converters.

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Eric J.Carlson received the B.S.and M.S.degrees from the University of Washington,Seattle,in 2006and2008,respectively.He was awarded the Grainger Foundation fellowship in2006,and the Robert Rushmer fellowship in2008.

He joined National Semiconductor in2009,where he works in the Mobile Devices Power pision. His technical interests include:energy harvesting, DC-DC converters,and power management for low-power wireless

circuits.

Kai Strunz received the Dipl.-Ing.degree from the

University of Saarland,Saarbrücken,Germany,in

1996,and the Dr.-Ing.degree(summa cum laude)

from the same university in2001.

From1995to1997,he pursued research at Brunel

University in London.From1997to2002,he worked

at the Division Recherche et Développement of Elec-

tricitéde France(EDF)in the Paris area.From2002

to2007,he was Assistant Professor of Electrical En-

gineering at the University of Washington in Seattle.

Since September2007,he has been Professor for Sus-tainable Electric Networks and Sources of Energy at Technische Universit?t Berlin,Germany.

Dr.Strunz received the 7ca2db25bcd126fff7050b31ard Martin Award from Saarland University in2002,the National Science Foundation(NSF)CAREER Award in2003,and the Outstanding Teaching Award from the Department of Electrical Engineering of the University of Washington in

2004.

Brian P.Otis(S’96–M’05)received the B.S.degree

in electrical engineering from the University of

Washington,Seattle,and the M.S.and Ph.D.degrees

in electrical engineering from the University of

California,Berkeley.

He joined the faculty of the University of

Washington as Assistant Professor of electrical

engineering in2005.His primary research interests

are ultra-low power radio-frequency integrated-cir-

cuit design and bioelectrical interface circuits and

systems.He previously held positions at Intel Cor-poration and Agilent Technologies.

Dr.Otis is an Associate Editor of the IEEE T RANSACTIONS ON C IRCUITS AND S YSTEMS P ART II:E XPRESS B RIEFS.He received the National Science Founda-tion CAREER award in2009and the U.C.Berkeley Seven Rosen Funds award for innovation in2003,and was co-recipient of the2002ISSCC Jack Raper Award for an Outstanding Technology Directions Paper.

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