广播电台整点报时

第一篇：广播电台整点报时

周一至周五整点报时

06：00一日之计在于晨，一天中的美好时光从早上开始。

07：00早上七点，新的一天找到新的动力。

07：00匆忙的早晨一袋牛奶、一只鸡蛋加上几片面包它就能为您提供一上午的能量。现在是早上7点。 08：00在工作和学习开始之前，喝杯水，它能促进代谢，帮助醒脑。现在是早上8点。

09：00繁忙而紧张的工作需要理清头绪，今天你做到了吗？现在是北京时间9点整

10：00工作中带着微笑，让微笑感染周围的人。现在是北京时间上午10点整。

11：00忙了一上午，抽个空，远眺下远方的绿色让眼睛得到适当的休息，现在是上午十一点。 12：00又是一个交通小高峰，回家路上注意安全！现在是北京时间中午12点整。

13：00午休小憩一会儿，下午的工作将事半功倍。现在是北京时间下午1点整。

14：00喝杯浓茶，振作精神，下午两点，有音乐的陪伴让工作更顺畅。

15：00事都有着多面性，换个方向，或许你能发现更多答案。现在是下午三点。

16：00在忙碌中找寻休憩，在平淡中找寻快乐。多一些快乐，少一丝束缚。现在是下午四点 17：00关爱他人，从小事开始。现在是北京时间下午5点整。

18：00下班高峰期，注意行车安全。现在是北京时间旁晚6点。

19：00关注时事动态，了解新闻大事，新闻联播更精彩。

20：00在城市的夜空下，欣赏喧嚣的夜晚，现在是晚上八点。

21：00让时间承载记忆，让岁月留下印记。现在是北京时间晚上9点整。

22：00喝一杯牛奶，融化一天的疲倦。现在是北京时间晚上10点整。

23：00寂静的深夜，依旧有好声音陪伴。现在是北京时间晚上11点整。

24：00静谧的午夜，道一声：“晚安"。现在是晚上12点。

工作张弛有度，生活追求品质，

第二篇：广 播 电 台

广 播 电 台

双簧：嘀嘀嘀嘀，哆！刚才最后一响是北京时间...看不清楚。长沙市哈利油广播电台，短波二百五，中波不管三七二十一，调口味立体声现在已经开始播音啦。首先请您欣赏每周一歌，为什么叫做每周一歌咧，就是说，有一个妹子，每周换一个满哥（小伙子）。请您欣赏长沙市著名歌星杨奇志演唱的——《中华造谣》：诶，杨家大爹哎豆鼓炒辣椒 奇 志（起身）：出来，你唱的这是中华民谣？

大 兵：这是长沙民谣。

奇志：谁教你的。

大兵：我爷爷。

奇志：你爷爷教你的儿歌也不卫生啊，现在电台电视上，有些歌曲让你感到莫名其妙，

什么我的爱赤裸裸，请你勾引我，这都播出了，你播出点健康歌曲。

大兵：好啦 那我唱首我外婆告诉我唱的，东方红。

奇志：太好了 这首歌曲我们老百姓非常热爱。

大兵：那我就唱我外婆那味道了

双簧：接下来，为您演唱一首,东~方~红,首先,我把歌词朗诵一遍:东方红,太阳升,中国出

了个毛泽东,#￥%@..咿呀呀..咿呀呀..#￥%@..

奇志（起身）：咿呀呀，你给我出来，你说的是法国话吧你。

大兵：什么法国话，这是湘乡话。

奇志：湘乡话说东方红怎么说成个，东~方~红。

大兵：我湘乡人讲话就这个味道，东方红 ，太阳升，中国出了个毛泽东。 奇志：他怎么里头还有个咿呀呀，干什么的这是。

大兵：咿呀呀，那是我外婆念着毛主席，咿呀呀~她要叫，你还管得她住啊。 奇志：你这节目主持人应该，普通话来朗诵。

大兵：好咯，普通话。普通话，吓到你就别怪我啦。

双簧：长沙市哈利油广播电台，现在是广告节目时间。朋友，你想吃烤红薯吗？烤红薯

气味芳香，价格烂便宜，含有丰富的维生素ABCDEFG，批发地点，五一广场，吓死这路弯里。朋友你需要卫生纸吗？请选用我们厂生产的刮得痛牌---砂纸。朋友，您想减肥吗？我向您介绍一套最新颖的减肥操，伸出你的双手，搭下来，瞪起你的对子眼，把舌头伸出来，再伸长一点，预备，起！左左右右，上上下下，快速喘气，叫两声，叫两声，汪汪！

奇志（起身）：我咬死你！

第三篇：芜湖广播电台

您现在的位置是：中刊首页>>芜湖人民广播电台交通广告>>媒体刊例

媒体名称：《芜湖人民广播电台交通广告》省份：安徽省 城市：芜湖市 录入日期：2012-02-17段位 T1

12:10 12:27 12:55

T1

17:27 17:55

T2 T2

18:10 18:30

2012年常规广告价格表 一:品牌类（单位:元/次）

5秒

时段

广告发布点位

20字

07:27 07:55 12:10

T1

12:27 12:55 17:27 17:55

7:10 8:20 11:27

T2

11:55 17:05 18:10 18:30

9:43 10:05 10:27

T3

10:55 11:05 13:13 8:30 8:55 9:05 9:27

A

18:55 19:05 19:27 19:55 13:27 13:55 15:05 15:25

B

15:55 16:05 16:27 16:55 06:27 14:05 14:27 14:55

C

20:05 20:27 20:55 21:27 21:55 05:30 05:55 22:27 22:55

D

23:27 23:55 24:00

广告创意费500元/条

二:套播类（单位:元/天）

5秒

名称 TB1 TB2 TB3 TB4 TB5 TB6

段位

20字

1T21T32A3B3C（每天10次）赠3D 1T32A3B3C（每天9次）赠3D 2A3B3C（每天8次）赠2D 1A3B3C（每天7次）赠2D 3B3C(每天6次）赠1D 2B3C（每天5次）赠1D

400 330 280 240 190 150

40字 860 740 640 550 460 380

60字 1230 1060 920 780 650 530

80字 1490 1290 1110 950 780 640

100字 1800 1560 1340 1150 950 770

120字 2030 1750 1500 1280 1050 870

10秒

15秒

20秒

25秒

30秒

广告录制费500元/条

20

70

90

110

130

150

30

80

110

130

160

180

40

90

130

160

190

210

50

100

150

180

220

250

60

110

160

200

240

270

70

130

180

220

270

310

80

140

200

250

300

340

40字

60字

80字

100字

120字

10秒

15秒

20秒

25秒

30秒

7:10 8:20 11:27 11:55 17:05

70

130

180

220

310

70

130

180

220

310

80

140

200

250

340

播出时间 07:27 07:55

80

140

200

250

340

5秒

10秒

15秒

20秒

30秒

TB1～TB3套播（10天起播）TB4～TB6套播（15天起播）赠送时段不得变换其他时段

备注

1.播出广告应遵守《中华人民共和国广告法》的有关规定，需先付款，手续齐备后方可播出； 2.T

1、T2段广告，同时段播出第二次时，在原价的基础上加收30%，播出第三次加收50%； 3.播出的广告，不得选择隔日播出或双休日不播的广告发布方式；

4.广告播出时长（含新上或中途更换内容），最高不得超出合同约定时长2秒；

5.单笔、次广告，低于刊例价6000元，不享受优惠；

6.受直播节目的影响，以上标明时间点允许存在前后10分钟的偏差。

芜湖广播电台2012.2.17

第四篇：多功能数字钟课程设计整点报时与闹钟功能VHDL代码

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all;

entity timkeeper is

Port ( up,setpin,upclk,settime,run : in std_logic;

a0,a1,b0,b1,c0,c1 : out std_logic_vector(3 downto 0);

result: out std_logic); end timkeeper;

architecture Behavioral of timkeeper is

component h_m_s_time port(

clk0,clk1,ce : in std_logic;

sec0,sec1 : buffer std_logic_vector(3 downto 0);

lock : in std_logic_vector(2 downto 0);

up : in std_logic; min0,min1 : buffer std_logic_vector(3 downto 0); hour0,hour1 : buffer std_logic_vector(3 downto 0); ov : out std_logic

); end component; component date port(

clk0,clk1,ce : in std_logic;

lock : in std_logic_vector(2 downto 0);

up : in std_logic;

mon0,mon1,year0,year1 : in std_logic_vector(3 downto 0);

date0,date1 : buffer std_logic_vector(3 downto 0);

ov : out std_logic

);

end component; component month_year port(

clk0,clk1,ce : in std_logic;

lock : in std_logic_vector(2 downto 0);

up : in std_logic;

mon0,mon1 : buffer std_logic_vector(3 downto 0);

year0,year1 : buffer std_logic_vector(3 downto 0)

); end component; component LED_disp port(

lock : in std_logic_vector(2 downto 0);

sec0,sec1,min0,min1,hour0,hour1 : in std_logic_vector(3 downto 0);

date0,date1,mon0,mon1,year0,year1 : in std_logic_vector(3 downto 0);

a0,a1,b0,b1,c0,c1 : out std_logic_vector(3 downto 0)

); end component; component alarm Port (

hour1,hour0,min1,min0,sec1,sec0 : in std_logic_vector(3 downto 0);

settime,run : in std_logic;

result : out std_logic); end component;

signal Tlock:std_logic_vector(2 downto 0); signal Tsecond_wave:std_logic; signal Tsec0,Tsec1,Tmin0,Tmin1,Thour0,Thour1:std_logic_vector(3 downto 0); signal Tdate0,Tdate1,Tmon0,Tmon1,Tyear0,Tyear1:std_logic_vector(3 downto 0); signal Tovday,Tovmonth:std_logic; signal vcc:std_logic; begin vcc<='1'; process(setpin) begin

if rising_edge(setpin) then

Tlock<=Tlock+'1';

end if;

end process;

u2:h_m_s_time port map(Tsecond_wave,upclk,vcc,Tsec0,Tsec1,Tlock,up,

Tmin0,Tmin1,Thour0,Thour1,Tovday); u3:date port map(Tovday,upclk,vcc,Tlock,up,Tmon0,Tmon1,Tyear0,Tyear1,

Tdate0,Tdate1,Tovmonth); u4:month_year port map(Tovmonth,upclk,vcc,Tlock,up,Tmon0,Tmon1,Tyear0,Tyear1); u5:LED_disp port map(Tlock,Tsec0,Tsec1,Tmin0,Tmin1,Thour0,Thour1,Tdate0,

Tdate1,Tmon0,Tmon1,Tyear0,Tyear1,a0,a1,b0,b1,c0,c1); u6:alarm port map (Tsec0,Tsec1,Tmin0,Tmin1,Thour0,Thour1,settime,run ,result); end Behavioral;

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; use work.pac.all; entity alarm is

Port ( hour1,hour0,min1,min0,sec1,sec0 : in std_logic_vector(3 downto 0);

settime,run : in std_logic;

result : out std_logic); end alarm;

architecture Behavioral of alarm is signal dhour1,dhour0,dmin1,dmin0,dsec1,dsec0:std_logic_vector(3 downto 0); begin p0:process(settime)

begin

if settime='1'then

dhour1<=hour1;

dhour0<=hour0;

dmin1<=min1;

dmin0<=min0;

dsec1<=sec1;

dsec0<=sec0;

end if;

end process p0; p1:process(run)

begin if run='1'then

if hour1=dhour1 and hour0=dhour0 and min1=dmin1 and min0=dmin0 and sec1=dsec1 and sec0 =dsec0 then

result<='1';

else result<='0';

end if; else result<='0'; end if;

end process p1; end Behavioral; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; use work.pac.all; entity date is

Port ( clk0,clk1,ce : in std_logic;

lock : in std_logic_vector(2 downto 0);

up : in std_logic;

mon0,mon1,year0,year1 : in std_logic_vector(3 downto 0);

date0,date1 : buffer std_logic_vector(3 downto 0);

ov : out std_logic); end date;

architecture Behavioral of date is signal tempy0:std_logic_vector(1 downto 0); signal tempy1,clk:std_logic; signal Td0,Td1:std_logic_vector(3 downto 0); begin tempy0<=year0(1 downto 0);tempy1<=year1(0); Td0<=date0;Td1<=date1; u1:process(lock,clk0,clk1)

begin

if(lock="000" or lock="001") then clk<=clk0;

else clk<=clk1;

end if;

end process u1;

u2:process(clk,ce)

begin

if rising_edge(clk) then

if(ce='1') then

if(lock="000") or (lock="001") or (lock="100" and up='1') then

if(mon0="0010" and mon1="0000") then

Feb_add_day(Td0,Td1,tempy0,tempy1,date0,date1);

elsif((mon0="0001" and mon1="0000") or (mon0="0011" and or( mon0="0101" and mon1="0000") or(mon0="0111" and mon1="0000")

mon1="0000")

or (mon0="1000" and mon1="0000") or(mon0="0000"and mon1="0001") or (mon0="0010" and mon1="0001")) then

oddmonth_add_day(Td0,Td1,date0,date1);

else evenmonth_add_day(Td0,Td1,date0,date1);

end if;

end if;

if(lock="100" and up='0') then

if(mon0="0010" and mon1="0000") then

Feb_sub_day(Td0,Td1,tempy0,tempy1,date0,date1);

elsif((mon0="0001" and mon1="0000") or (mon0="0011" and mon1="0000") or(mon0="0101" and mon1="0000") or

(mon0="0111" and mon1="0000") or (mon0="1000" and mon1="0000") or(mon0="0000" and mon1="0001") or (mon0="0010"

and mon1="0001")) then

oddmonth_sub_day(Td0,Td1,date0,date1);

else evenmonth_sub_day(Td0,Td1,date0,date1);

end if;

end if;

end if;

end if;

end process u2;

u3:process(ce)

begin

if rising_edge(clk) then

if(lock/="000" and lock/="001") then

ov<='0';

elsif(ce='1') then

if(mon0="0010" and mon1="0000") then

if((tempy1='0' and tempy0="00") or (tempy1='1' and tempy0="10")) then

if(date0="1001" and date1="0010") then

ov<='1';

else ov<='0';

end if;

elsif(date0="1000" and date1="0010") then ov<='1'; else ov<='0'; end if;

elsif((mon0="0001" and mon1="0000") or(mon0="0011" and mon1="0000") or (mon0="0010" and mon1="0000")

or (mon0="0111" and mon1="0000")or (mon0="1000" or(mon0="0000" and mon1="0001")

or (mon0="0010" and mon1="0001")) then

if(date0="0001" and date1="0011") then

ov<='1';

else ov<='0';

end if;

elsif(date0="0000" and date1="0011") then

ov<='1';

else ov<='0';

end if;

end if;

end if;

end process u3; end Behavioral; library IEEE; use IEEE.STD_LOGIC_1164.ALL;

and

mon1="0000") use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; use work.pac.all; entity h_m_s_time is

Port ( clk0,clk1,ce : in std_logic;

sec0,sec1 : buffer std_logic_vector(3 downto 0);

lock : in std_logic_vector(2 downto 0);

up : in std_logic;

min0,min1 : buffer std_logic_vector(3 downto 0);

hour0,hour1 : buffer std_logic_vector(3 downto 0);

ov : out std_logic); end h_m_s_time;

architecture Behavioral of h_m_s_time is signal Ts0,Ts1,Tm0,Tm1,Th0,Th1:std_logic_vector(3 downto 0); signal clk:std_logic; begin

Ts0<=sec0;Ts1<=sec1;Tm0<=min0;Tm1<=min1;Th0<=hour0;Th1<=hour1; u1: process(lock,clk0,clk1)

begin

if(lock="000" or lock="001") then

clk<=clk0;

else clk<=clk1;

end if;

end process u1;

u2: process(clk,lock)

begin

if rising_edge(clk) then

if(ce='1') then

if(lock="000")or(lock="001")or(lock="111" and up='1') then

addsec_addmin(Ts0,Ts1,sec0,sec1);

end if;

if(lock="111" and up='0') then

subsec_submin(Ts0,Ts1,sec0,sec1);

end if;

if(lock="000" or lock="001") then

if(sec0="1001" and sec1="0101") then

addsec_addmin(Tm0,Tm1,min0,min1);

end if;

if(sec0="1001" and sec1="0101" and min0="1001" and min1="0101") then

addhour(Th0,Th1,hour0,hour1);

end if;

if(sec0="1001" and sec1="0101" and min0="1001" and min1="0101"

and hour0="0011" and hour1="0010") then

ov<='1';

else ov<='0';

end if;

end if;

if(lock="110" and up='1') then

addsec_addmin(Tm0,Tm1,min0,min1);

end if;

if(lock="101" and up='0') then

subsec_submin(Tm0,Tm1,min0,min1);

end if;

if(lock="101" and up='1') then

addhour(Th0,Th1,hour0,hour1);

end if;

if(lock="101" and up='0') then

subhour(Th0,Th1,hour0,hour1);

end if;

end if;

end if;

end process u2; end Behavioral; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all;

entity LED_disp is

Port ( lock : in std_logic_vector(2 downto 0);

sec0,sec1,min0,min1,hour0,hour1 : in std_logic_vector(3 downto 0);

date0,date1,mon0,mon1,year0,year1 : in std_logic_vector(3 downto 0);

a0,a1,b0,b1,c0,c1 : out std_logic_vector(3 downto 0)); end LED_disp;

architecture Behavioral of LED_disp is begin process(lock,sec0,sec1,min0,min1,hour0,hour1,date0,date1,mon0,mon1,year0,year1)

begin

if(lock="000") then

a0<=sec0;a1<=sec1;b0<=min0;b1<=min1;c0<=hour0;c1<=hour1;

end if;

if(lock="000") then

a0<=sec0;a1<=sec1;b0<=min0;b1<=min1;c0<=hour0;c1<=hour1;

end if;

if(lock="001") then

a0<=date0;a1<=date1;b0<=mon0;b1<=mon1;c0<=year0;c1<=year1;

end if;

if(lock="101") then

a0<="0000";a1<="0000";b0<="0000";b1<="0000";c0<=hour0;c1<=hour1;

end if;

if(lock="110") then

a0<="0000";a1<="0000";b0<=min0;b1<=min1;c0<="0000";c1<="0000";

end if;

if(lock="111") then

a0<=sec0;a1<=sec1;b0<="0000";b1<="0000";c0<="0000";c1<="0000";

end if;

if(lock="010") then a0<="0000";a1<="0000";b0<="0000";b1<="0000";c0<=year0;c1<=year1; end if; if(lock="011") then

a0<="0000";a1<="0000";b0<=mon0;b1<=mon1;c0<="0000";c1<="0000";

end if;

if(lock="100") then

a0<=date0;a1<=date1;b0<="0000";b1<="0000";c0<="0000";c1<="0000";

end if;

end process; end Behavioral; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; use work.pac.all; entity month_year is

Port ( clk0,clk1,ce : in std_logic;

lock : in std_logic_vector(2 downto 0);

up : in std_logic;

mon0,mon1 : buffer std_logic_vector(3 downto 0);

year0,year1 : buffer std_logic_vector(3 downto 0)); end month_year;

architecture Behavioral of month_year is signal Ty0,Ty1,Tm0,Tm1:std_logic_vector(3 downto 0); signal clk:std_logic; begin

Ty0<=year0;Ty1<=year1;Tm0<=mon0;Tm1<=mon1; u1: process(lock,clk0,clk1)

begin

if(lock="000" or lock="001") then

clk<=clk0;

else clk<=clk1;

end if;

end process u1; u2:process(clk,ce) begin if rising_edge(clk) then

if (ce='1') then

if(lock="000")or(lock="001")or(lock="011" and up='1') then

add_month(Tm0,Tm1,mon0,mon1);

end if;

if(lock="011" and up='0') then

sub_month(Tm0,Tm1,mon0,mon1);

end if;

if(lock="000" or lock="001") then

if(mon0="0010" and mon1="0001")then

add_year(Ty0,Ty1,year0,year1);

end if;

end if;

if(lock="010" and up='1')then

add_year(Ty0,Ty1,year0,year1);

end if;

if(lock="010" and up='0')then

sub_year(Ty0,Ty1,year0,year1);

end if;

end if;

end if;

end process u2;

end Behavioral; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;

package pac is

procedure add_year(oldyear0,oldyear1:in std_logic_vector;

signal newyear0:out std_logic_vector;

signal newyear1:out std_logic_vector); procedure add_month(oldmonth0,oldmonth1:in std_logic_vector;

signal newmonth0:out std_logic_vector;

signal newmonth1:out std_logic_vector); procedure sub_month(oldmonth0,oldmonth1:in std_logic_vector;

signal newmonth0:out std_logic_vector;

signal newmonth1:out std_logic_vector); procedure sub_year(oldyear0,oldyear1:in std_logic_vector;

signal newyear0:out std_logic_vector;

signal newyear1:out std_logic_vector); procedure Feb_add_day(oldday0,oldday1:in std_logic_vector;

ty0:in std_logic_vector(1 downto 0);

ty1:in std_logic;

signal newday0:out std_logic_vector;

signal newday1:out std_logic_vector); procedure Feb_sub_day(oldday0,oldday1:in std_logic_vector;

ty0:in std_logic_vector(1 downto 0);

ty1:in std_logic;

signal newday0:out std_logic_vector;

signal newday1:out std_logic_vector); procedure oddmonth_add_day(oldday0,oldday1:in std_logic_vector;

signal newday0:out std_logic_vector;

signal newday1:out std_logic_vector); procedure oddmonth_sub_day(oldday0,oldday1:in std_logic_vector;

signal newday0:out std_logic_vector;

signal newday1:out std_logic_vector); procedure evenmonth_add_day(oldday0,oldday1:in std_logic_vector;

signal newday0:out std_logic_vector;

signal newday1:out std_logic_vector); procedure evenmonth_sub_day(oldday0,oldday1:in std_logic_vector;

signal newday0:out std_logic_vector;

signal newday1:out std_logic_vector); procedure addsec_addmin(oldtime0,oldtime1:in std_logic_vector;

signal newtime0:out std_logic_vector;

signal newtime1:out std_logic_vector); procedure subsec_submin(oldtime0,oldtime1:in std_logic_vector;

signal newtime0:out std_logic_vector;

signal newtime1:out std_logic_vector); procedure addhour(oldhour0,oldhour1:in std_logic_vector;

signal newhour0:out std_logic_vector;

signal newhour1:out std_logic_vector); procedure subhour(oldhour0,oldhour1:in std_logic_vector;

signal newhour0:out std_logic_vector;

signal newhour1:out std_logic_vector); end pac; package body pac IS procedure add_year(oldyear0,oldyear1:in std_logic_vector;

signal newyear0:out std_logic_vector;

signal newyear1:out std_logic_vector)is

begin

if(oldyear0="1001" and oldyear1/="1001")then

newyear0<="0000";newyear1<=oldyear1+'1';

else newyear0<=oldyear0+'1';

end if; if oldyear0="1001" and oldyear1="1001" then newyear0<="0000";

newyear1<="0000"; end if; end add_year;

procedure add_month(oldmonth0,oldmonth1:in std_logic_vector;

signal newmonth0:out std_logic_vector;

signal newmonth1:out std_logic_vector)is

begin

if oldmonth0="0010" and oldmonth1="0001" then newmonth0<="0001";

newmonth1<="0000";

elsif oldmonth0="1001" then newmonth0<="0000";

newmonth1<=oldmonth1+'1'; else

newmonth0<=oldmonth0+'1'; end if; end add_month; procedure sub_month(oldmonth0,oldmonth1:in std_logic_vector;

signal newmonth0:out std_logic_vector; signal newmonth1: out std_logic_vector) is begin

if oldmonth0="0001"and oldmonth1="0000"then

newmonth0<="0010";newmonth1<="0001";

elsif oldmonth0="0000" and oldmonth1="0001" then

newmonth0<="1001";newmonth1<= oldmonth1-'1'; else newmonth0<=oldmonth0-'1'; end if; if oldmonth0="0000" and oldmonth1="0000"then

newmonth0<="0010";newmonth1<="0001";

end if;

end sub_month; procedure sub_year(oldyear0,oldyear1:in std_logic_vector; signal newyear0: out std_logic_vector; signal newyear1: out std_logic_vector) is

begin if oldyear0="0000"then

if oldyear1="0000"then

newyear1<="1001"; else newyear1<= oldyear1-'1'; end if; newyear0<="1001"; else newyear0<=oldyear0-'1'; end if; end sub_year; procedure Feb_add_day(oldday0,oldday1:in std_logic_vector;

Ty0:in std_logic_vector(1 downto 0);

Ty1:in std_logic;

signal newday0: out std_logic_vector;

signal newday1: out std_logic_vector) is

begin

if oldday0="1000"and oldday1="0010"then

if((Ty1='0' and Ty0="00") or (ty1='1' and ty0="10"))then

newday0<=oldday0 +'1'; else newday0<="0001";newday1<="0000"; end if; elsif oldday0="1001" and oldday1="0010"then

newday0<="0001";newday1<="0000"; elsif oldday0="1001" then

newday0<="0000";newday1<=oldday1+'1'; else newday0<=oldday0+'1'; end if; end Feb_add_day;

procedure Feb_sub_day(oldday0,oldday1:in std_logic_vector;

Ty0:in std_logic_vector(1 downto 0);

Ty1:in std_logic;

signal newday0: out std_logic_vector;

signal newday1: out std_logic_vector) is

begin

if (oldday0="0000" or oldday0="0001") and oldday1="0000"then

if((Ty1='0' and Ty0="00") or (ty1='1' and ty0="10"))then

newday0<="1001";newday1<="0010";

else newday0<="1000";newday1<="0010";

end if;

elsif oldday0="0000" and oldday1/="0000"then

newday0<="1001";newday1<=oldday1-'1'; else newday0<=oldday0-'1'; end if; end Feb_sub_day; procedure oddmonth_add_day(oldday0,oldday1:in std_logic_vector;

signal newday0: out std_logic_vector;

signal newday1: out std_logic_vector) is

begin

if( oldday0="0001" and oldday1="0011")then

newday0<="0001";newday1<="0000";

elsif oldday0="1001"then

newday0<="0000";newday1<=oldday1+'1';

else newday0<= oldday0+'1';

end if;

end oddmonth_add_day; procedure oddmonth_sub_day(oldday0,oldday1:in std_logic_vector;

signal newday0: out std_logic_vector;

signal newday1: out std_logic_vector) is

begin

if( oldday0="0001" or oldday0="0000")and oldday1="0000" then

newday0<="0001";newday1<="0011";

elsif oldday0="0000" and oldday1/="0000" then

newday0<="1001";newday1<=oldday1-'1';

else newday0<= oldday0-'1';

end if;

end oddmonth_sub_day; procedure evenmonth_add_day(oldday0,oldday1:in std_logic_vector;

signal newday0: out std_logic_vector;

signal newday1: out std_logic_vector) is

begin

if oldday0="0000" and oldday1="0011" then newday0<="0001";

newday1<="0000";

elsif oldday0="1001"then

newday0<="0000";

newday1<=oldday1+'1';

else newday0<=oldday0+'1';

end if;

end evenmonth_add_day; procedure evenmonth_sub_day(oldday0,oldday1:in std_logic_vector;

signal newday0:out std_logic_vector;

signal newday1:out std_logic_vector)is begin

if (oldday0="0000" or oldday0="0001") and oldday1="0000"then

newday0<="0000";

newday1<="0011"; elsif oldday0="0000" and oldday1/="0000"

then newday0<="1001";

newday1<=oldday1- '1'; else

newday0<=oldday0- '1';

end if; end

evenmonth_sub_day;

procedure addsec_addmin(oldtime0,oldtime1:in std_logic_vector;

signal newtime0:out std_logic_vector;

signal newtime1:out std_logic_vector)is

begin

if

(oldtime0="1001")then

newtime0<="0000";

if (oldtime1="0101")then

newtime1<="0000";

else newtime1<=oldtime1+'1';

end if;

else newtime0<=oldtime0+'1';

end if;

end addsec_addmin; procedure subsec_submin(oldtime0,oldtime1:in std_logic_vector;

signal newtime0:out std_logic_vector;

signal newtime1:out std_logic_vector)is begin

if (oldtime0="0000")then

newtime0<="1001";

if (oldtime1="0000")then

newtime1<="0101";

else newtime1<=oldtime1-'1';

end if;

else newtime0<=oldtime0-'1';

end if;

end

subsec_submin; procedure addhour(oldhour0,oldhour1:in std_logic_vector;

signal newhour0:out std_logic_vector;

signal newhour1:out std_logic_vector)is begin

if (oldhour0="1001")then

newhour0<="0000";

newhour1<=oldhour1+'1';

else newhour0<=oldhour0+'1';

end if;

if oldhour0="0011" and oldhour1="0010"then

newhour0<="0000"; newhour1<="0000";

end if;

end

addhour; procedure subhour(oldhour0,oldhour1:in std_logic_vector;

signal newhour0:out std_logic_vector;

signal newhour1:out std_logic_vector)is begin if oldhour0="0000" then

newhour1<=oldhour1-'1';newhour0<="1001";

else newhour0<=oldhour0-'1';

end if;

if oldhour0="0000" and oldhour1="0000"then

newhour0<="0011"; newhour1<="0010";

end if;

end

subhour; end pac; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all;

entity second_wave is

Port ( f1000 : in std_logic;

second_wave1 : buffer std_logic); end second_wave;

architecture Behavioral of second_wave is signal cnt:std_logic_vector(8 downto 0); begin

process(f1000,cnt)

begin

if rising_edge(f1000) then

if(cnt="111110011") then

cnt<="000000000";second_wave1<=not second_wave1;

else cnt<=cnt+'1';

end if;

end if;

end process; end Behavioral; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all;

entity settime is

Port ( hour1,hour0,min1,min0,sec1,sec0 : in std_logic_vector(3 downto 0);

mytime,run : in std_logic;

result : out std_logic); end settime;

architecture Behavioral of settime is signal dhour1,dhour0,dmin1,dmin0,dsec1,dsec0:std_logic_vector(3 downto 0); begin p0:process(mytime)

begin

if mytime='1'then

dhour1<=hour1;

dhour0<=hour0;

dmin1<=min1;

dmin0<=min0;

dsec1<=sec1;

dsec0<=sec0;

end if;

end process p0; p1:process(run)

begin if run='1'then

if hour1=dhour1 and hour0=dhour0 and min1=dmin1 and min0=dmin0 and sec1=dsec1 and sec0 =dsec0 then

result<='1';

else result<='0';

end if; else result<='0'; end if;

end process p1; end Behavioral;

第五篇：广播电台实习报告

本人于年在人民广播电台实习了半个月，期间获益良多。在实习过程中，我担任了电台采编，参与各类节目的编辑与稿件采写。

在最初的一段时间内，我了解了广播电台的运作模式。广播电台一天的工作是忙碌的。虽然依照上级安全要求不能制作直播节目，但为了制作出优秀的录播节目，建瓯广播电台始终都在高速运转中。一个节目的从创意到制作完成，一篇广播稿从筹划到最后敲定，都要经过层层把关，凝聚了电台人员的辛勤汗水。

这半个月来我还是学到很多的。由于专业知识的缺陷，最开始自己只能够试着写稿，但根本达不到要求。在电台里，各位员工都是十分忙碌的，谁也没有闲暇的时间来对我进行指导，我只能靠自己阅读书籍来进步。台里一些叔叔阿姨也给了我很大帮助。在写稿方面，我体会到了广播新闻的一系列自身特点，广播稿的写法也不同于一般的新闻稿，广播新闻一般比较口语化，导语需要能够立即让人听懂，整条新闻要宜听而不是宜看。在学习写稿的过程中，台里的叔叔阿姨还建议我做剪贴本，多搜集好的新闻稿件，多听多看，这样才能在业务上有所进步。在实习期间我还参与了广播节目的制作，由于专业知识有限，我只能负责搜集背景资料，网络，报刊媒体成了我搜集的资源。在实习的后期，我学会了一些设备的操控，开始尝试进行节目后期的录音编辑。但由于实习时间有限，我不得不结束了在建瓯人民广播电台的实习。

半个月的实习让我零距离接触了新闻单位，尝试了专业的新闻工作，让我体会自己与真正新闻工作者之间的巨大差距。要成为一名合格的新闻工作者是不容易的，我只有在学校期间努力学习新闻专业知识，在假期积极实践，才能够尽早成为一名优秀的新闻工作者。

年月日至月日期间，我在人民广播电台进行了为期7天的实习。

一走进电台的新闻部办公室，我就被他忙碌的气氛所感染。自从放假以来，我在家一直过着睡到自然醒的懒散生活，见到这番忙碌景象，竟一下子手足无措起来，还好有位魏佳姐姐帮我安排好座位。手里捧着杯热水，心也稍稍安定了些。我的实习生活就这样在一杯开水的陪伴下温暖的开始了。

电台领导并没有安排什么具体工作给我，所以我就自由的观察起新闻部的各项工作。第一天我跟魏姐参观了录播室、直播室、监控室，大体了解了播音员、导播以及编辑们的主要工作内容。新闻部有十几个工作人员，每个人都身兼数职的忙碌着，顾不上吃早饭的也大有人在。播音员的工作绝非只是动动嘴就行的清闲活。一条听起来再普通不过的广告有时也要录上四五遍，还要时刻注意怎样调整气息才能让声音听起来底气十足。主播陈亮的一句玩笑话道出了这个表面风光的职业私下的辛苦——“播音员没有感冒的资格”。任何行业都有自己的艰辛，也许我们理想中那种轻松加愉快的行业并不存在。尽管有时会因为忙于应考而抱怨，，但现在却深感作为学生的轻松自在。

实习第五天，我跟着魏姐到市环保局做专题采访。原定的采访对象是局长，但由于准备不到位，只能先跟一位主任就采访内容进行具体讨论。魏姐提出的问题首先由主任进行审核，最终五个问题并成了三个。采访过程与我想象的相差甚远，既没有“杨澜访谈录”的知性，也没有“艺术人生”的感性。小小的采访在没有见到原定采访对象的情况下在主任的办公室里耗掉了两个小时，我在一旁听着，逐渐失去耐性……主任的烟瘾很大，一直烟不离手，可看魏姐一副恭敬有佳的样子，我也只好耐心的听下去。在三个小时的采访结束后，我带着满身的烟味离开了办公室。

实习只有短短七天，虽然没有学到什么专业的技能，但一番体验让我感觉收益良多。当有一天我走出校门踏入单位，不会有人再把我看作小孩子，同事会很自然的称我“小周”，而我也必须担负起我的责任。一脸的幼稚让我现在在单位显得有些格格不入，但我也相信，总有一天我会真正成熟起来，在岗位上胜任我的工作！

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