Techniques for High Performance Digital Frequency Synthesis and Phase Control

Techniques for High-Performance Digital

Frequency Synthesis and Phase Control

by

Chun-Ming Hsu

Bachelor of Science in Engineering

National Taiwan University,June1997

Master of Science

National Taiwan University,June1999

Submitted to the Department of Electrical Engineering and Computer

Science

in partial ful?llment of the requirements for the degree of Doctor of Philosophy in Electrical Engineering and Computer Science

at the

MASSACHUSETTS INSTITUTE OF TECHNOLOGY

September2008

c Massachusetts Institute of Technology2008.All rights reserved. Author..............................................................

Department of Electrical Engineering and Computer Science

August27,2008 Certi?ed by..........................................................

Michael H.Perrott,Ph.D.

Associate Professor of Electrical Engineering

Thesis Supervisor Accepted by.........................................................

Terry P.Orlando,Ph.D.

Chairman,Committee on Graduate Students Department of Electrical Engineering and Computer Science

2

Techniques for High-Performance Digital Frequency

Synthesis and Phase Control

by

Chun-Ming Hsu

Submitted to the Department of Electrical Engineering and Computer Science

on August27,2008,in partial ful?llment of the

requirements for the degree of

Doctor of Philosophy in Electrical Engineering and Computer Science

Abstract

This thesis presents a3.6-GHz,500-kHz bandwidth digital?Σfrequency synthesizer architecture that leverages a recently invented noise-shaping time-to-digital converter (TDC)and an all-digital quantization noise cancellation technique to achieve excellent in-band and out-of-band phase noise,respectively.In addition,a passive digital-to-analog converter(DAC)structure is proposed as an e?cient interface between the digital loop?lter and a conventional hybrid voltage-controlled oscillator(VCO)to create a digitally-controlled oscillator(DCO).An asynchronous divider structure is presented which lowers the required TDC range and avoids the divide-value-dependent delay variation.The prototype is implemented in a0.13-μm CMOS process and its active area occupies0.95mm2.Operating under1.5V,the core parts,excluding the VCO output bu?er,dissipate26mA.Measured phase noise at3.67GHz achieves-108 dBc/Hz and-150dBc/Hz at400kHz and20MHz,respectively.Integrated phase noise at this carrier frequency yields204fs of jitter(measured from1kHz to40MHz).

In addition,a3.2-Gb/s delay-locked loop(DLL)in a0.18-μm CMOS for chip-to-chip communications is presented.By leveraging the fractional-N synthesizer tech-nique,this architecture provides a digitally-controlled delay adjustment with a?ne resolution and in?nite range.The provided delay resolution is less sensitive to the process,voltage,and temperature variations than conventional techniques.A new ?Σmodulator enables a compact and low-power implementation of this architecture.

A simple bang-bang detector is used for phase detection.The prototype operates at a1.8-V supply voltage with a current consumption of55mA.The phase resolution and di?erential rms clock jitter are1.4degrees and3.6ps,respectively.

Thesis Supervisor:Michael H.Perrott,Ph.D.

Title:Associate Professor of Electrical Engineering

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Acknowledgments

I would like to acknowledge many people for helping me during my doctoral work. First,I would especially like to thank my advisor,Professor Michael Perrott,for his continuous inspiration and encouragement on this work.It has been an exciting and valuable experience to work with him.I appreciate for what he has pushed me during the past few years,such that I could accomplish my dissertation and degree within a reasonable period of time.

I thank my committee,Professor Anantha Chandrakasan and Professor Joel Daw-son,for their generous time and commitment.I also thank Professor Vladmir Sto-janovic who supervised my RQE together with Professor Chandrakasan.

I need to thank my academic advisor,Professor Harry Lee,for his professional advise on my courses and schedule from my?rst day at MIT.

I am very grateful for having wonderful groupmates;I owe each of them a lot. Min Park and Kerwin Johnson did the wire bonding for me again and again.Matt Straayer generously allowed me to use his GRO design.He also contributed many useful suggestions on my work.Charlotte Lau provided me a lot of information about MIT and the group even before I came to Boston.She also shared her VCO design with me as well as drew the layout for part of my DLL chip.Belal Helal designed the shift-register for the group;without this cell,I might have missed the deadline of my synthesizer tape-out.Matt Park has been a good friend who has always heard my complaint.In addition,he and Min Park also introduced a lot of delicious Korean food to me.Scott Meneinger and Ethan Crain were also a great help to me in my ?rst year.

I extend my thanks to many friends in MTL and EECS,especially Joyce Kwong, Vivienne Sze,and Yogesh Ramadass,with whom I went through the tough classes together in my?rst year.

I’d like to thank C2S2,the Focus Center for Circuit and System Solutions,one of?ve centers funded under FCRP,and SRC program,as well as MIT Center for Integrated Circuit and System for funding my research.In addition,Mr.Peter

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Holloway helped me to access the process in National Semiconductor for my DLL chip.

I also need to thank for our group administrator,Valerie DiNardo,and all of the MTL sta?.

The experts in MIT writing center,who helped me edit this dissertation,is also a wonderful resource to me.

I should also thank my former advisor,Professor Shen-Iuan Liu,in National Tai-wan University for his continuous help.Professor Chorng-Kuang Wang in NTU also shared much of his life experience with me.

I thank my friends,no matter in Taiwan or in the States,who have been very supportive.I owe a special note of gratitude to Wei-Hung Chen for his valuable suggestions and help during my graduate-school application.In addition,I would like to especially thank Chi-Heng Wang,Ya-Ting Chou,Da-Yuan Tung,Hsin-Ning Keng,Hsin-Pei Shih,Yu-Chen Yeh,Chen-Hsiang Yu,and Julie Leh,who have brought me a lot of joy and pleasure in Boston.I will never forget those precious memories which have been built up with you.

Last but not least,I would like to share this pride with my family members.Dad and Mom-Thank you for what you have educated me.Also,your support all the time made it easier for me to pursue my dream.My wife Wan-Chen,to whom this dissertation is dedicated,-Thank you for always accompanying with me and cheering me up whenever I was down.Without you,life at MIT would be horrible.

There are still many others to thank as well.Thus,I would like to share this dissertation with those who have ever helped,in?uenced,and inspired me in my life.

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Contents

1Introduction21

1.1Area of focus (22)

1.2Proposed Digital Frequency Synthesis Technique (22)

1.2.1Overview (23)

1.2.2Quantization Noise Cancellation (23)

1.2.3Digital-to-Analog Converter (25)

1.2.4Divider (26)

1.2.5Loop Filter (27)

1.3Proposed Digital Phase Control Technique (27)

1.3.1Overview (28)

1.3.2Synthesizer-based Phase Shifter (30)

1.3.3?ΣModulator (30)

1.4Contributions (31)

1.5Overview of Thesis (32)

2Proposed Techniques for Achieving a Low-Noise and Wide-Bandwidth Digital PLL35

2.1Background (35)

2.2Challenge of a Low-noise Wide-bandwidth Digital PLL (40)

2.3Review of the Gated Ring Oscillator TDC (44)

2.4Review of the Previous Noise Cancellation Techniques in an Analog PLL47

2.5Proposed Digital Noise Cancellation Technique (50)

2.6Proposed Digital?ΣFractional-N Synthesizer (52)

7

2.7Summary (56)

3Digital-to-Analog Converter for VCO Control57

3.1Passive Digital-to-Analog Converter (58)

3.1.1DAC Operation (58)

3.1.2Design Considerations and Implementation Details (59)

3.1.3Settling Time Calculation (64)

3.1.4Noise Calculation (67)

3.2Hybrid VCO (72)

3.3DCO Model (76)

3.4Summary (77)

4Asynchronous Divider79

4.1Asynchronous,Low-Jitter Divider (79)

4.1.1Divider Operation (81)

4.1.2Implementation Details (83)

4.2The TDC Unwrapping Function (90)

4.3TDC O?set (93)

4.4Summary (94)

5PLL System Design95

5.1System Design Using PLL Design Assistant (95)

5.2?ΣModulator Design (97)

5.3PLL Type and Order (100)

5.4Proposed Loop Filter (101)

5.5Calculation of the Loop Filter Parameters (105)

5.6Summary (110)

6Noise Analysis and Behavior Simulation111

6.1Noise Analysis of the Proposed Digital Synthesizer (111)

6.1.1PLL Noise Modeling (111)

6.1.2Overall Phase Noise Calculation (115)

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6.2Design Considerations (121)

6.2.1PLL Bandwidth (121)

6.2.2Reference Frequency (123)

6.2.3Bandwidth of the Coarse-tuning DAC (124)

6.2.4Coarse-tuning VCO Gain (125)

6.3Behavior Simulation with CppSim (126)

6.4Summary (128)

7Digital Synthesizer Measurement133

7.1Area and Power Dissipation (133)

7.2VCO Gain (135)

7.3Phase Noise and Spurs (137)

7.4Locking Time (146)

7.5Comparison (147)

7.6Improved phase noise at20MHz o?set (151)

7.7Summary (152)

8Proposed Techniques for Digital Phase Control153

8.1Background (153)

8.2Proposed DLL Architecture (156)

8.2.1Synthesizer-based Phase Shifter (156)

8.2.2?ΣModulator (162)

8.2.3Bang-bang Detector (167)

8.3Circuit Implementation (168)

8.4Results (170)

8.5Summary (172)

9Conclusion175

9.1Thesis Summary (175)

9.2Future Research (179)

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List of Figures

1-1Detailed block diagram of the proposed digital?Σsynthesizer (24)

1-2Simpli?ed view of the all-digital quantization noise cancellation (24)

1-3Simpli?ed schematic of the proposed DAC (25)

1-4Proposed asynchronous divider structure achieving low power and jitter.26 1-5Coarse/?ne tuning of the PLL output frequency (28)

1-6Proposed DLL with a synthesizer-based phase shifter (29)

1-7Proposed synthesizer-based phase shifter (30)

1-8Multi-rate implementation of the proposed?Σarchitecture (31)

2-1Integer-N frequency synthesizer (36)

2-2?Σfractional-N synthesizer (37)

2-3A wider PLL bandwidth results in less quantization noise suppression.38 2-4Progression from analog to digital PLL implementation (39)

2-5Phase noise of narrow-BW and wide-BW digital PLLs (41)

2-6Classical time-to-digital converter in[1] (41)

2-7Phase noise performance:(a)50-kHz BW and20-ps TDC resolution

(b)500-kHz BW and20-ps TDC resolution.(c)500-kHz BW,6-ps TDC

resolution,and20-dB?Σnoise cancellation (43)

2-8Concept of a gated ring oscillator TDC[2] (45)

2-9Concept of a multipath gated ring oscillator TDC (46)

2-10The prototype synthesizer in this thesis uses the multipath gated ring oscillator TDC in[3] (47)

2-11Model of the GRO TDC (47)

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2-12GRO causes another two noises other than the quantization noise (48)

2-13Classical phase noise cancellation PLL (48)

2-14A digital PLL allows noise cancellation in the digital domain without the need for analog components (50)

2-15All-digital quantization noise cancellation:(a)simpli?ed view of cir-cuits,(b)settling behavior of the scale factor (51)

2-16Proposed digital?Σsynthesizer utilizing the GRO TDC and the all-digital noise cancellation (53)

2-17Detailed block diagram of the proposed digital?Σsynthesizer (54)

2-18Predicted PLL noise performance using a multipath GRO TDC and an all-digital noise cancellation.(The thermal and?icker noises of the

GRO are ignored.) (55)

2-19Predicted PLL noise performance including thermal and?icker noises of the GRO (55)

3-1DAC operation:(a)step one:the unit capacitors are charged.(b)step two:the charges are redistributed and?ltered (60)

3-2Implementation details of the proposed DAC (61)

3-3Switch:(a)schematic(b)simulated on-resistance(c)device size (62)

3-4Timing diagram of the non-overlapping clocks (63)

3-5DAC schematic for time constant calculation (65)

3-6Simpli?ed schematic for time constant calculation (66)

3-7Simulated transient responses of Figures3-5,3-6,and3-8when M=N=16.67 3-8Equivalent circuit to extract time constants of Figures3-5and3-6..67 3-9Simulated transient responses of Figures3-6and3-8when M=16and N=31 (68)

3-10Equivalent circuit for noise analysis (68)

3-11Calculated spectral noise density usingα=2.5,f c=50MHz,C1=1 pF,R on2=2200ohm/32 (70)

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3-12Calculated,approximated,and simulated noise densities usingα=2.5,

f c=50MHz,C1=1pF,R on2=2200ohm/32 (71)

3-13Calculated,approximated,and simulated noise densities usingα=20,

f c=50MHz,C1=1pF,R on2=2200ohm/32 (71)

3-14Schematic of the hybrid VCO (72)

3-15Simpli?ed structure of the accumulation-mode varactor (73)

3-16The switch structure in[4]is used in the four-bit MIM array (75)

3-17Bu?ers after VCO to drive the divider and the output pad (75)

3-18Model of the proposed DCO (76)

4-1Classical approach to using an asynchronous divider in a digital fractional-N PLL (80)

4-2The GRO output is not well-de?ned when one reference cycle includes

(a)no stop edge(b)two stop edges (81)

4-3Proposed asynchronous divider structure achieving low power and jitter.82 4-4Schematic of the modular divider structure (84)

4-5Schematic of the divide-by-two/three stage in[5] (85)

4-6TSPC implementation of the divide-by-two/three stage (86)

4-7Timing diagram of the divide-by-16-to-31divider(a)main signals(b)MOD

(d)control qualifer (87)

signals(c)CON?

i

4-8Detailed schematic of the proposed divider structure (88)

4-9A three-bit counter used to control the multiplexer and to record the number of divider edges (89)

4-10Simulated jitter of the divide-by-16-to-32divider (90)

4-11Simulated jitter of the resampled reference clock:(a)N1toggles be-tween19and21,N2=N3=N0=20(b)N2toggles between19and

21,N1=N3=N0=20(c)N3toggles between19and21,N1=N2=

N0=20(d)N0toggles between19and21,N1=N2=N3=20 (91)

4-12A phase unwrapping function eliminates the phase wrapping at the TDC output (92)

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4-13Timing diagram when phase wrapping occurs(a)f stop

f start (92)

4-14Implementation of the TDC unwrapping function (93)

4-15The time di?erence between the GRO start and stop edges is biased to an o?set value in the steady state (94)

5-1Parameters assumed in this PLL analysis (96)

5-2Noise analysis using PLL Design Assistant (97)

5-3Phase noise of a PLL using a third-order?Σmodulator without noise cancellation (98)

5-4Phase noise of a PLL using a second-order?Σmodulator without noise cancellation (98)

5-5Phase noise of a PLL using a second-order?Σmodulator with20-dB noise cancellation (99)

5-6Phase noise of a PLL using a second-order?Σmodulator with26-dB noise cancellation (100)

5-7The delays on both paths need to be equal to each other such that the quantization noise can be cancelled correctly (100)

5-8Coarse/?ne-tuning of the PLL output frequency (102)

5-9Fine-tuning digital loop?lter (103)

5-10Coarse-tuning digital loop?lter (104)

5-11The bandwidth of the coarse-tuning DAC needs to be su?ciently higher than the targeted zero frequency (105)

5-12Modeling of the PLL in the?ne-tuning mode for the PLL response calculation (106)

5-13Modeling of the PLL in the coarse-tuning mode for the PLL response calculation (108)

6-1Modeling of the proposed digital synthesizer with various noise sources.112 6-2Dividing the noise sources into two groups:reference-referred noise and DCO-referred noise (114)

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6-3Calculation of the reference-referred noise (114)

6-4Calculation of the DCO-referred noise (115)

6-5Overall calculated noise using the parameters in Table6.1 (120)

6-6Overall calculated noise assuming a1-MHz bandwidth (122)

6-7Overall calculated noise with a26-MHz reference clock (124)

6-8Calculated noise when the bandwidth of the coarse-tuning DAC is set to3MHz (125)

6-9Calculated noise when the coarse-tuning VCO gain is reduced to20 MHz/V (126)

6-10CppSim behavior model of the proposed digital synthesizer (127)

6-11Simulated coarse-tuning and?ne-tuning voltages (128)

6-12Zoomed-in coarse-tuning and?ne-tuning voltages (129)

6-13Simulated scale factor and phase error signal e[k]with the noise can-cellation enabled at t=15μs (130)

6-14Comparison between the calculated noise with MATLAB and simu-lated noise with CppSim (131)

6-15Ten phase noise simulation results with a5%device standard deviation.132

7-1The active area of the implemented0.13-μm digital frequency synthe-sizer is0.95mm2 (134)

7-2Photo of the evaluation board (134)

7-3Power distribution of the chip (135)

7-4Measured frequency range of the DCO(?ne-tuning code is set to512).136 7-5Measured DCO frequency at band7and the extracted coarse-tuning analog VCO gain(The?ne-tuning code is set to512) (137)

7-6Measured DCO frequency at band7and the extracted?ne-tuning ana-log VCO gain(The coarse-tuning code is set to825) (138)

7-7Measured DCO phase noise at3.67GHz (138)

7-8Measured PLL phase noise at3.67GHz (139)

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7-9Comparison between the measured and calculated noises with the noise cancellation (140)

7-10Comparison between the measured and calculated noises without the noise cancellation (141)

7-11Measured PLL phase noise at3.638GHz (142)

7-12Comparison between the measured and calculated noises at3.638GHz.143 7-13Measured jitter and phase noise at400kHz o?set over a50-MHz range with1-MHz increments (143)

7-14Measured reference spur when the VCO frequency is3.67GHz (144)

7-15Measured worst-case fractional spurs over a50-MHz range with1-MHz increments (145)

7-16Measured worst-case fractional spurs when the carrier frequency is less than1MHz away from3.65GHz (145)

7-17Measured fractional spur when the VCO frequency is(a)3.651GHz

(b)3.6504GHz (146)

7-18Measured phase noise at3.67GHz with a30.5-MHz reference clock..147 7-19Measured phase noise at4.135GHz with a50-MHz reference clock..148 7-20Measured settling time achieves10-ppm accuracy in less than20μs..148 7-21Frequency toggles between two levels after the coarse-tuning is performed.149 7-22A modi?ed chip improves phase noise at20MHz o?set (152)

8-1DLL with an analog phase interpolator (154)

8-2Phase interpolator controlled by current DACs (155)

8-3Proposed DLL with a synthesizer-based phase shifter (156)

8-4VCO-based phase shifter (157)

8-5Proposed synthesizer-based phase shifter (158)

8-6Comparison of the?Σsynthesizer and proposed phase shifter (159)

8-7Synthesizer-based phase shifter including circuits to generate control pulses (160)

8-8Phase-shifting operation without up/down counter over?ow (161)

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8-9Improving resolution by increasing the number of bits of the hardware.161 8-10Phase-shifting operation with up/down counter over?ow (162)

8-11An over?ow detector can remove the undesired negative pulse (163)

8-12Modi?ed?Σarchitecture with less circuit complexity (163)

8-13Multi-rate implementation of the proposed?Σarchitecture (165)

8-14Simple implementation of the di?erentiator and adders (165)

8-15The synthesizer noise model and phase interpolation operation (167)

8-16Conventional bang-bang detector architecture (168)

8-17Proposed bang-bang detector architecture (168)

8-18Schematic of the DLL (170)

8-19Die photo of the DLL chip (171)

8-20Recovered eye-diagram with a3.2-Gb/s input data(a)Single-ended data and clock(b)di?erential clock (173)

8-21Recovered eye-diagram with a1.6-Gb/s input data (174)

9-1The other potential implementation of the digital noise cancellation..180 9-2A dual-path PLL architecture (181)

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List of Tables

6.1Parameters used for calculation in Figure6-5 (121)

7.1Measured Current Dissipation (136)

7.2Comparison Among Published Digital Synthesizers (149)

7.3Comparison Among Published Analog Noise Cancellation Synthesizers151

8.1Measured Single-ended RMS Clock/Data Jitter (171)

8.2Measured Di?erential Clock Jitter (172)

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Chapter1

Introduction

As the capability of the digital calculation keeps on improving in modern sub-micron CMOS processes,there is increasing interest in developing digital approaches to assist or even replace the analog functions that encounter design di?culties due to the de-grading analog device characteristics such as decreasing g m r o and supply voltage,and increasing leakage current and variation.People have demonstrated some successful results in various digitally-assisted analog subsystems including data converters,RF transceivers,and phase-locked loops(PLL)[6][7][8][9].

Among various digitally-assisted analog techniques,the digital PLL has especially become a very hot research topic in the past few years after it was demonstrated to be able to meet the stringent wireless communication speci?cations[9][10][11][12][13]. However,existing low-noise digital fractional-N synthesizer techniques can only achieve about a50-kHz loop bandwidth that may be not wide enough for some new applica-tions[9][12].Therefore,the goal of this research is to achieve a low-noise fractional-N PLL with a wider bandwidth and a mostly digital implementation[14].Furthermore, we apply the fractional-N PLL technique to a new application:phase control of a high-speed clock[15].

The remainder of this chapter presents an overview of this thesis.We begin by narrowing the focuses of the thesis.Next,the proposed techniques are brie?y discussed with implementation highlights.After that,the contributions of this thesis are summarized.Finally,an outline of the thesis is presented.

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