数字电路课程设计报告-同步N进制计数器的设计与仿真

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2 同步时序逻辑电路的设计方

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同步N进制计数器的设计与仿真

摘 要：本课程设计首先从一般方法入手，介绍了同步时序电路设计的方法过程，然后将此方法

应用于同步二进制电路的设计，再在同步二进制计数器的基础上进行分析给出十三进制电路状态方程、卡诺图，得到带进位输出端得十三进制计数器的设计，最后用MUX+plus2对所得电路进行仿真，验证设计，并对电路延时等性能进行分析。

关键词： 同步时序逻辑电路，同步二进制计数器，带进位输出端得十三进制计数器，MUX+plus2

Synchronous N into system design and simulation of the counter

Abstract: Our course is designed from the general method of first, which introduced the synchronization

method of sequential circuits design process, and then the method is used in synchronous binary circuit design, and on the basis of synchronous binary counter analysis given ten ternary circuit state equation, cano figure, to get a carry the output to ten ternary counter design, final with MUX + plus2 of the circuit, and simulation test design, and the circuit such as delay performance analysis.

Keywords: synchronous sequential logic circuit, synchronous binary counters, binary counter thirteen

with carry out , MUX+plus2

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1 引言

计数器是用来累计时钟脉冲个数的时序逻辑部件，在数字电路中，我们把记忆输入CP脉冲个数的操作叫做计数，把能实现计数状态的电子电路称为计数器。计数器也是数字系统中用途最广泛的基本部件之一，几乎在各种数字系统中都有计数器。它不仅可以计数，还可以对CP脉冲分频，以及构成时间分配器或时序发生器，对数字系统进行定时、程序控制操作。此外，还能用它执行数字运算，是数字电路中使用最多的一种时序逻辑电路。计数器不仅能用于对时钟脉冲计数，还可以用于分频、定时，产生节拍脉冲和脉冲序列以及进行数字运算等。计数器的种类很多，从不同的角度出发，有不同的分类方法：按照计数进位制的不同，可分为二进制计数器、十进制计数器和N进制计数器；按照计数器中的触发器是否同时动作分类，可把计数器分为同步计数器和异步计数器；按照计数器中所表示的数字的变化规律是递增还是递减来分，有加法计数器、减法计数器和可逆计数器(递增计数的称为加法计数器，递减计数的称为减法计数器，既可递增又可递减的称为可逆计数器)。

目前市场上所具有的计数器大多是二进制或是十进制计数器，而较少使用十三进制的计数器，除非是在专用的集成电路中，因此设计性能好、速度快的十三进制计数器是有一定市场前景的。目前主要采用两种设计方法来进行计数器的设计，第一种为采用传统的硬件电路设计方法来设计硬件，第二种为采用HDL语言来设计系统硬件。电子设计自动化的普及与CPLD/FPGA器件的广泛应用，使得计数器的设计变得非常容易。其中可编程计数器使用方便，灵活，能满足工程上的多种应用。

计数器是时序电路但也有其特点：第一，计数器一般将触发器的输出直接构成电路的输出，在分析电路时往往只有状态方程而没有输出方程。第二，计数器电路直接将时钟信号作为输入信号。除了时钟信号以外，大部分电路没有其他输入。尽管计数器有上述特点，对他们的分析方法还是与其他时序电路一样，只是状态图和状态表略有不同。

本文中先对同步时序电路的一般方法进行介绍，然后根据一般方法设计带进位输出端的十三进制计数器电路，最后用MUX+plus2对电路进行仿真验证并分析其性能。

2 同步时序逻辑电路的设计方法

2.1 同步时序逻辑电路的概述

与组合逻辑电路不同，时序电路具有记忆功能，并且当时的输出和信号的历史有关，所以时序电路中除了包含组合逻辑电路之外，还包含有记忆单元。记忆单元的输出逻辑组合被称为时序电路的状态。状态只有在驱动信号来到之时发生改变。无论是时钟驱动还是事件驱动，在两次驱动间隔期间，系统的状态保持不变。

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x1x2y1z1组合电路Y1记忆电路z2y2Y2

图 1 时序电路的基本框架

时序电路又可以细分为摩尔型和米利型：摩尔模型中，时序电路在tk时刻的输出仅于当时刻的现态有关，而与当前输入无关。米利模型中，时序电路在tk时刻的输出不仅与现态有关，并且与tk时刻的输入也有关。

输入变量激励输出变量组合电路时钟记忆电路（触发器）组合电路

图2 同步时序电路的米利模型

输入变量激励组合电路

时钟记忆电路（触发器）输出变量组合电路

图3 同步时序电路的摩尔模型

本课程设计中所要设计的计数器的工作特点是在时钟信号操作下自动地依次从一个状态转为下一个状态，所以它没有输入逻辑变量，只有进位输出信号。因此是属于摩尔型的一种简单时序电路。

2.2 同步时序逻辑电路的一般设计方法

① 分析电路的功能要求或者时序图，设计描述该电路的有限状态机

任何一个同步时序电路，在大多数情况下问题是以自然语言描述的，所以电路设计的第一步也

是最为关键的一步，就是通过分析自然语言所能表达的功能要求，列出该问题的状态转换表或者状态转换图。

状态状态转换表或者状态转换图实际上可以表达该时序电路的所有信息，这样描述的时序电路也称为状态机。时序电路通常可以用一个通用模型来表示，就是有限状态机。所谓有限，是指在该

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